处理器BUCK电感Select要求¶
Key parameters of power inductor
Important
L(inductance value) = 4.7uH ± 20%, DCR(DC resistance) ≦ 0.4 ohm, Isat(saturation current) ≧ 450mA.
如何降低Standby power consumption¶
To meet the long battery life requirement of watch products, it is recommended to use load switches for dynamic power management of various functional modules in hardware design For always-on modules or paths, select appropriate devices to reduce static current.
During design, attention should be paid to controlling the hardware default state of the GPIO pins of the power switch, and M-level pull-up and pull-down resistors should be added to ensure that the load switch is off by default.
When selecting power devices, LDO and Load Switch chips with small static current Iq and shutdown current Istb should be chosen, especially for always-on power chips, the Iq parameter must be considered.
Processor operating modes and wake-up sources¶
Operating mode |
CPU |
Peripheral |
SRAM |
IO |
LPTIM |
Wake-up source |
Wake-up time |
|---|---|---|---|---|---|---|---|
Active |
Run |
Run |
Accessible |
可翻转 |
Run |
- |
- |
Sleep |
Stop |
Run |
Accessible |
可翻转 |
Run |
任意中断 |
<0.5us |
DeepSleep |
Stop |
Stop |
Inaccessible，Fully retained |
Level maintained |
Run |
RTC，Wake-up IO，GPIO，LPTIM，蓝牙 |
250us |
Standby |
Reset |
Reset |
Inaccessible，Fully retained |
Level maintained |
Run |
RTC，Wake-up IO，LPTIM，蓝牙 |
1ms |
Hibernate |
Reset |
Reset |
Inaccessible，Not retained |
High impedance |
Reset |
RTC，Wake-up IO |
>2ms |
Interrupt source |
Pin |
Detailed description |
|---|---|---|
LWKUP_PIN0 |
PA24 |
中断信号0 |
LWKUP_PIN1 |
PA25 |
中断信号1 |
LWKUP_PIN2 |
PA26 |
中断信号2 |
LWKUP_PIN3 |
PA27 |
中断信号3 |
LWKUP_PIN10 |
PA34 |
中断信号10 |
LWKUP_PIN11 |
PA35 |
中断信号11 |
LWKUP_PIN12 |
PA36 |
中断信号12 |
LWKUP_PIN13 |
PA37 |
中断信号13 |
LWKUP_PIN14 |
PA38 |
中断信号14 |
LWKUP_PIN15 |
PA39 |
中断信号15 |
LWKUP_PIN16 |
PA40 |
中断信号16 |
LWKUP_PIN17 |
PA41 |
中断信号17 |
LWKUP_PIN18 |
PA42 |
中断信号18 |
LWKUP_PIN19 |
PA43 |
中断信号19 |
LWKUP_PIN20 |
PA44 |
中断信号20 |
Clock¶
The chip requires two external clock sources, a 48MHz main crystal and a 32.768KHz RTC crystal. The specific specifications and selection of the crystals are as follows:
Important
晶体 |
Crystal specification requirements |
Detailed description |
|---|---|---|
48MHz |
CL≦12pF（推荐值7pF）△F/F0≦±10ppmESR≦30 ohms（推荐值22ohms） |
The power consumption of the crystal oscillator is related to CL and ESR. The smaller the CL and ESR, the lower the power consumption. For optimal power consumption performance, it is recommended to use the recommended values of CL≦7pF and ESR≦22 ohms.A parallel matching capacitor is reserved next to the crystal. When CL<9pF, no capacitor needs to be soldered |
32.768KHz |
CL≦12.5pF（推荐值7pF）△F/F0≦±20ppm ESR≦80k ohms（推荐值38Kohms） |
晶振功耗和CL,ESR相关,CL和ESR越小功耗越低，为了最佳功耗性能，建议采用推荐值CL≦9pF，ESR≦40K ohms.晶体旁边预留并联匹配电容,当CL<12.5pF时，无需焊接电容 |
Model |
Manufacturer |
Parameter |
|---|---|---|
E1SB48E001G00E |
Hosonic |
F0 = 48.000000MHz，△F/F0 = -6 ~ 8 ppm，CL = 8.8 pF，ESR = 22 ohms Max TOPR = -30 ~ 85℃，Package =（2016 公制） |
ETST00327000LE |
Hosonic |
F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm，CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制） |
SX20Y048000B31T-8.8 |
TKD |
F0 = 48.000000MHz，△F/F0 = -10 ~ 10 ppm，CL = 8.8 pF，ESR = 40 ohms Max TOPR = -20 ~ 75℃，Package =（2016 公制） |
SF32K32768D71T01 |
TKD |
F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm，CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制） |
RF¶
The RF trace requires a characteristic impedance of 50ohms. If the antenna is well matched, no additional components are needed on the RF. It is recommended to reserve a π-type matching network for spurious filtering or antenna matching during design.
Display¶
The chip supports 3-Line SPI, 4-Line SPI, Dual data SPI, Quad data SPI, and serial JDI interfaces. It supports 16.7M-colors (RGB888), 262K-colors (RGB666), 65K-colors (RGB565), and 8-color (RGB111) color depth modes. The maximum supported resolution is 512RGBx512.
SPI/QSPI display interface¶
The chip supports 3/4-wire SPI and Quad-SPI interfaces to connect to LCD displays. The signal descriptions are shown in the table below.
SPI signal |
Pin |
Detailed description |
|---|---|---|
CSx |
PA03 |
Enable signal |
WRx_SCL |
PA04 |
Clock signal |
DCx |
PA06 |
Data/command signal in 4-wire SPI mode, Data 1 in Quad-SPI mode |
SDI_RDx |
PA05 |
Data input signal in 3/4-wire SPI mode, Data 0 in Quad-SPI mode |
SDO |
PA05 |
Data output signal in 3/4-wire SPI mode should be shorted to SDI_RDX |
D[0] |
PA07 |
Data 2 in Quad-SPI mode |
D[1] |
PA08 |
Data 3 in Quad-SPI mode |
RESET |
PA00 |
Reset display signal |
TE |
PA02 |
Tearing effect to MCU frame signal |
JDI display interface¶
芯片支持并行JDI接口来连接LCDDisplay屏，如下表所示。
SPI signal |
Pin |
Detailed description |
|---|---|---|
CSx |
PA03 |
Enable signal |
WRx_SCL |
PA04 |
Clock signal |
DCx |
PA06 |
Data/command signal in 4-wire SPI mode, Data 1 in Quad-SPI mode |
SDI_RDx |
PA05 |
Data input signal in 3/4-wire SPI mode, Data 0 in Quad-SPI mode |
SDO |
PA05 |
Data output signal in 3/4-wire SPI mode should be shorted to SDI_RDX |
D[0] |
PA07 |
Data 2 in Quad-SPI mode |
D[1] |
PA08 |
Data 3 in Quad-SPI mode |
RESET |
PA00 |
Reset display signal |
TE |
PA02 |
Tearing effect to MCU frame signal |
Touch and backlight interface¶
The chip supports an I2C format touch screen control interface and touch status interrupt input, and also supports one PWM signal to control the enable and brightness of the backlight power supply, as shown in the table below.
SPI signal |
Pin |
Detailed description |
|---|---|---|
CSx |
PA03 |
Enable signal |
WRx_SCL |
PA04 |
Clock signal |
DCx |
PA06 |
Data/command signal in 4-wire SPI mode, Data 1 in Quad-SPI mode |
SDI_RDx |
PA05 |
Data input signal in 3/4-wire SPI mode, Data 0 in Quad-SPI mode |
SDO |
PA05 |
Data output signal in 3/4-wire SPI mode should be shorted to SDI_RDX |
D[0] |
PA07 |
Data 2 in Quad-SPI mode |
D[1] |
PA08 |
Data 3 in Quad-SPI mode |
RESET |
PA00 |
Reset display signal |
TE |
PA02 |
Tearing effect to MCU frame signal |
Storage¶
Description of memory connection interface¶
The chip supports four types of external storage media: SPI Nor Flash, SPI NAND Flash, SD NAND Flash, and eMMC.
SPI signal |
Pin |
Detailed description |
|---|---|---|
CSx |
PA03 |
Enable signal |
WRx_SCL |
PA04 |
Clock signal |
DCx |
PA06 |
Data/command signal in 4-wire SPI mode, Data 1 in Quad-SPI mode |
SDI_RDx |
PA05 |
Data input signal in 3/4-wire SPI mode, Data 0 in Quad-SPI mode |
SDO |
PA05 |
Data output signal in 3/4-wire SPI mode should be shorted to SDI_RDX |
D[0] |
PA07 |
Data 2 in Quad-SPI mode |
D[1] |
PA08 |
Data 3 in Quad-SPI mode |
RESET |
PA00 |
Reset display signal |
TE |
PA02 |
Tearing effect to MCU frame signal |
SPI signal |
Pin |
Detailed description |
|---|---|---|
CSx |
PA03 |
Enable signal |
WRx_SCL |
PA04 |
Clock signal |
DCx |
PA06 |
Data/command signal in 4-wire SPI mode, Data 1 in Quad-SPI mode |
SDI_RDx |
PA05 |
Data input signal in 3/4-wire SPI mode, Data 0 in Quad-SPI mode |
SDO |
PA05 |
Data output signal in 3/4-wire SPI mode should be shorted to SDI_RDX |
D[0] |
PA07 |
Data 2 in Quad-SPI mode |
D[1] |
PA08 |
Data 3 in Quad-SPI mode |
RESET |
PA00 |
Reset display signal |
TE |
PA02 |
Tearing effect to MCU frame signal |
Startup settings¶
芯片支持内部合封Spi Nor Flash、外挂Spi Nor Flash、外挂Spi Nand Flash、外挂SD Nand Flash和外挂eMMC启动。其中：
SF32LB52AUx6 It has internally integrated flash and boots from the internally integrated flash by default
SF32LB52D/F/HUx6 It has internally integrated psram and must boot from external storage media
Bootstrap[1] (PA13) |
Bootstrap[0] (PA17) |
Boot From ext memory |
|---|---|---|
L |
L |
Spi Nor Flash |
L |
H |
Spi Nand Flash |
H |
L |
SD Nand Flash |
H |
H |
eMMC |
Power control of boot storage media¶
The chip supports power switch control of the boot storage medium to reduce power consumption when shutting down.The enable pin of the power switch must be controlled by PA21, and the enable level requirement is [high to open, low to close].
Important
SF32LB52AUx6 has internally integrated flash, please add a power switch to VDD_SIP.
SF32LB52D/F/HUx6 has internally integrated psram. If PVDD=3.3V and VDD_SIP is powered by internal LDO, VDD_SIP does not need a power switch if PVDD=1.8V, VDD_SIP needs a power switch.
The power supply for externally provided storage media is independent of VDD_SIP, and a separate power switch should be added.
The enable pin of the power switch for all memory related to startup must be controlled by PA21.
Button¶
Power on/off button¶
The PA34 of the chip supports the long-press reset function, which can be designed as a button to achieve the power on/off + long-press reset function.PA34的长按复位功能要求高电平有效，所以Design成默认下拉为低，Button按下后电平为高，如图 {number}所示。
Vibration motor¶
The chip supports PWM output to control the vibration motor.
Audio interface¶
芯片的音频相关接口，如表4-16所示，Audio interface信号有以下特点：
Supports single-ended ADC input, externally connected to an analog MIC, requiring a DC-blocking capacitor with a capacitance value of at least 2.2uF in between, and the power supply of the analog MIC connects to the MIC_BIAS power output pin of the chip.
Supports one differential DAC output, externally connected to an analog audio PA, the routing of the DAC output should follow differential line routing, ensuring proper ground shielding, also note that: Trace Capacitor < 10pF, Length < 2cm.
Audio signal |
Pin |
Detailed description |
|---|---|---|
BIAS |
MIC_BIAS |
Microphone power supply |
AU_ADC1P |
ADCP |
Single-ended analog MIC input |
AU_DAC1P |
DACP |
Differential analog output P |
AU_DAC1N |
DACN |
Differential analog output N |
模拟MEMS MIC推荐电路如图 {number}所示，模拟ECM MIC 单端推荐电路如图 {number}所示，其中MEMS_MIC_ADC_IN和ECM_MIC_ADC_IN连接到SF32LB52X的ADCP输入Pin。
模拟音频输出推荐电路如图 {number}所示，注意虚线框内的差分低通滤波器要靠近芯片端放置。
Sensor¶
The chip supports sensors such as heart rate, acceleration, and geomagnetic.The power supply for the sensors should use a Load Switch with a relatively small Iq for power switching control.
UART and I2C pin settings¶
The chip supports arbitrary pin mapping for UART and I2C functions, and all PA interfaces can be mapped to UART or I2C function pins.
GPTIM pin settings¶
The chip supports arbitrary pin mapping for GPTIM functions, and all PA interfaces can be mapped to GPTIM function pins.
Debug and download interface¶
The chip supports the DBG_UART interface for downloading and debugging, connecting to the PC via a UART to USB Dongle board with a 3.3V interface.The chip can output debug information through DBG_UART, for details please refer to the table{number} <sf32lb52x-B-P-JDI-LCD-table>
DBG信号 |
Pin |
Detailed description |
|---|---|---|
DBG_UART_RXD |
PA18 |
Debug UART Receive |
DBG_UART_TXD |
PA19 |
Debug UART Send |
产线烧录和晶体校准¶
Sparkle Technology provides an offline downloader to complete the production line program burning and crystal calibration，When designing the hardware, please note that at least the following test points should be reserved：PVDD、GND、AVDD33、DB_UART_RXD、DB_UART_RXD，PA01。
详细的烧录和晶体校准见“**_脱机下载器使用指南.pdf”文档，Included in the development materials package。
原理图和PCB图纸检查列表¶
见“Schematic checklist.xlsx”和“PCB checklist.xlsx”文档，Included in the development materials package。