SF32LB52x-Hardware Design Guide

Attention

This document is compatible with chips with the suffix numbers 0, 3, 5, and 7, uses lithium battery power supply, and supports USB charging。

For chips with the suffix letters B, E, G, J, H, they belong to the SF32LB52X series and use 3.3V power supply。应该参照Hardware Design Guide

基本介绍

The main purpose of this article is to help developers complete the development of watch solutions based on the SF32LB52x series chip。This article focuses on the precautions related to hardware design during the solution development process, aiming to minimize the workload of developers and shorten the product’s time to market。

SF32LB52x is a series of highly integrated, high-performance MCU chips for ultra-low power artificial intelligence Internet of Things (AIoT) scenarios。The chip adopts a big.LITTLE architecture based on the Arm Cortex-M33 STAR-MC1 processor, integrating a high-performance 2D/2.5D graphics engine, an artificial intelligence neural network accelerator, dual-mode Bluetooth 5.3, and an audio CODEC，It can be widely used in various application scenarios such as wristband wearable electronic devices, smart mobile terminals, and smart home。

Attention

SF32LB52x is the lithium battery powered version of the SF32LB52 series, with a power supply voltage of 3.2~4.7V, supporting charging，具体包含As followsModel：
SF32LB520U36，合封1MB QSPI-NOR Flash
SF32LB523UB6，合封4MB OPI-PSRAM
SF32LB525UC6，合封8MB OPI-PSRAM
SF32LB527UD6，合封16MB OPI-PSRAM

The peripheral resources of the processor are as follows：

• 44x GPIO

• 3x UART

• 4x I2C

• 2x GPTIM

• 2x SPI

• 1x I2S音频Interface

• 1x SDIO 存储Interface

• 1x PDM音频Interface

• 1x 差分模拟音频Output

• 1x 单端模拟音频Input

• Support单/双/四Data线SPIDisplayInterface，Support串行JDIModeDisplayInterface

• Support带GRAM和不带GRAM的两种Display screen

• SupportUART下载和软件调试

封装

Table2-1 Package information table

封装名称	尺寸	Pin间距
QFN68L	7x7x0.85 mm	0.35 mm

Diagram2-1 QFN68LPin分布

Typical application solutions

The figure below is a block diagram of a typical SF32LB52x sports watch composition, with main functions including display, storage, sensors, vibration motor, and audio input and output。

Diagram3-1 运动手Table组成框Diagram

Note

• A dual-core CPU architecture that balances high performance and low power consumption design requirements

• Integrated charging management and PMU module inside the chip

• Supports TFT or AMOLED displays with QSPI interface, with a maximum resolution of 512*512

• Supports PWM backlight control

• Supports external QSPI Nor/Nand Flash and SD Nand Flash memory chips

• Supports dual-mode Bluetooth 5.3

• Supports analog audio input

• Supports analog audio output

• Supports PWM vibration motor control

• Supports acceleration/geomagnetic/gyroscope sensors with SPI/I2C interface

• Supports heart rate/oxygen saturation/ECG/geomagnetic sensors with SPI/I2C interface

• Supports UART debugging print interface and burning tools

• Supports Bluetooth HCI debugging interface

• Supports one-to-many program burning in production lines

• Supports crystal calibration function in production lines

• Supports OTA online upgrade function

原理Diagram设计指导

Power

Processor power supply requirements

Table4-1 Power供电要求

PowerPin	最小电压(V)	典型电压(V)	最Large电压(V)	最Large电流(mA)	DetailedDescription
VBUS	4.6	5.0	5.5	500	VBUSPowerInput
VBAT	3.2	-	4.7	500	VBATPowerOutput
VCC	3.2	-	4.7	500	系统PowerInput(1)
VSYS	-	3.3	-	500	VSYSPowerOutput(2)
BUCK_LX	-	1.25	-	50	BUCKOutput脚，接电感
BUCK_FB	-	1.25	-	50	BUCK反馈和内部PowerInput脚，接电感另一端，且外挂Capacitance
VDD_VOUT1	-	1.1	-	50	内部LDO，外挂Capacitance，内部Power，不给外设供电
VDD_VOUT2	-	0.9	-	20	内部LDO，外挂Capacitance，内部Power，不给外设供电
VDD_RET	-	0.9	-	1	内部LDO，外挂Capacitance，内部Power，不给外设供电
VDD_RTC	-	1.1	-	1	内部LDO，外挂Capacitance，内部Power，不给外设供电
VDD18_VOUT	-	1.8	-	30	SIPPower(3) 内部Power，不给外设供电，关闭LDO时，可以外供
VDD33_VOUT1	-	3.3	-	150	3.3V LDO Output1(4)，默认无Output，需要软件配置才有3.3VOutput
VDD33_VOUT2	-	3.3	-	150	3.3V LDO Output2，默认无Output，需要软件配置才有3.3VOutput
AVDD33_AUD	2.97	3.3	3.63	50	3.3V音频PowerInput
AVDD_BRF	2.97	3.3	3.63	100	RFPowerInput
MIC_BIAS	1.4	-	2.8	-	MICPowerOutput

Note

⁽¹⁾ VCC power input, lithium battery power supply, default software setting for low voltage = 3.48V When using constant voltage power supply, the power supply range is 3.6

⁽²⁾ VSYSPower，给AVDD_BRF供电

⁽³⁾ VDD18_VOUTPower
SF32LB520U36，外供3.3VPower
SF32LB523UB6，SF32LB525UC6，SF32LB527UD6，使用内部LDO，不需要外供Power
软件设置时要根据芯片Model来配置内部的VDD18 LDO，外供Power时，不要开启

⁽⁴⁾ VDD33_VOUT1Power
SF32LB520U36，只给VDD18_VOUT、外挂Flash和AVDD33_AUD供电
SF32LB523UB6，SF32LB525UC6，SF32LB527UD6，只给外挂Flash和AVDD33_AUD供电

处理器BUCK电感选择要求

功率电感关键Parameters

Important

L(电感值) = 4.7uH ± 20%，DCR(直流Impedance) ≦ 0.4 ohm，Isat(饱和电流) ≧ 450mA。

电池及充电控制

充电Circuit有两种使用情景：外部充电管理芯片和片内集成充电管理模块。

外部充电管理芯片

外部充电管理芯片分为两种Type：一种是不带PPM（Power路径管理）功能，一种是带PPM功能。Diagram4-1是使用不带PPM功能的充电芯片的典型充电CircuitDiagram，电池直接给SF32LB52x的VBAT和VCCPin供电。Diagram4-2是使用带PPM功能的充电芯片的典型充电CircuitDiagram，充电芯片的VSYS给SF32LB52x的VCCPin供电，充电芯片的VBATConnect到电池和SF32LB52xVBATPin。这两种方案都是通过SF32LB52x的VBATPin来测量电池的电压值。VBATPin内部集成了一路GPADC，可以采集VBAT的电压值，采样精度+/-30mV以内。

Diagram4-1 Schematic diagram of external charging chip circuit without PPM function

Diagram4-2 Schematic diagram of external charging chip circuit with PPM function

片内集成充电管理模块

When using the built-in integrated charging management module of SF32LB52x, as shown in Figure 4 - 3, when the battery is low and shuts down, after inserting the charger, the battery needs to be charged to the boot voltage before the system can start normally and display the charging interface.

Diagram4-3 Schematic diagram of integrated charging management circuit

Selection of OVP chip when using the built - in integrated charge management module

SF32LB52x VBUSPinInput电压范围：4.5V ~ 5.5V，所以只能选择下面两个Type的OVP芯片

• OVP chip with adjustable OVLO，参考芯片ModelAW32905FCR

• OVP chip with Regulator output，参考芯片ModelSGM4064YDE8G，LP5305AQVF

Diagram4-4是OVP chip with adjustable OVLO的典型应用CircuitDiagram，其中OVP芯片的Output电压VIN_OVLO要设定为5.2V~5.5V之间，计算时要考虑芯片和电阻的误差。具体公式为：

Requirement: The error of VOVLO_TH should be ≦3%, and the resistance error of R1 and R2 should be ≦1%

Diagram4-4 Application circuit diagram of OVP chip with adjustable OVLO

Diagram4-5是RegulatorOutput的OVP芯片的典型应用CircuitDiagram，其中OVP芯片的Regulator固定Output小于5.5V，用来给SF32LB52x的VBUSPin供电。

要求：OVP芯片的LDOOutput电压在4.5V ~ 5.4V

Diagram4-5 Application circuit diagram of OVP chip with Regulator output

Precautions for the use of internal charging management module and integrated LDO

Important

Precautions for the use of SF32LB52x internal integrated charging management module：

• VBUS的Input电压范围：4.6V~5.5V

• VCC的Input电压范围：3.2V~4.7V

• Charger默认的涓流电流是56mA

• Charger默认的涓流到恒流的转变电压值是3.0V

• Charger默认的恒流电流是65mA，Support调整，调整范围5~560mA

• Charger默认的充满电压是4.2V，Support调整，HighestSupport4.45V满电电压

• Charger的复充电压为满电电压值-0.15V

• 充电器VBUS上至少要提供350mA的供电能力

• Note意VBUS路径上的直流Impedance，不易过Large，整个充电过程中最Large电流时，芯片VBUSPin的电压值不能低于4.6V

• 采用无线充时，请确保无线充的供电能力Large于恒流充电电流。

Precautions for the use of SF32LB52x integrated LDO：

• 内部集成的VDD33_VOUT1，VDD33_VOUT2的Output路径上，Capacitance之和不能超过9.6uF

• AVDD33_AUD只能使用VDD33_VOUT1供电，不能使用VSYS

• LCD不能使用内部LDO供电，需要使用外部LDO供电

How to reduce standby power consumption

In order to meet the long - term battery life requirement of watch products, it is recommended to use load switches for dynamic power management of various functional modules in hardware design If it is a normally - on module or path, choose appropriate devices to reduce static current.

如Diagram4-6Shown，Typical power structure diagram of SF32LB52x system中，推荐VDD33_VOUT2给Motor供电，VDD33_VOUT1给外部Flash和Sensor等外设供电，LCD采用外加的LDO供电。

设计时要Note意控制Power开关的GPIOPin的硬件默认状态，同时AddM级阻值的上下拉电阻，保证Load开关默认关闭。

PowerDevice选型上，LDO和Load Switch 芯片要选择Static电流Iq和关断电流Istb都小的Device，特别是常开的Power芯片一定要关Note下IqParameters。

Diagram4-6 SF32LB52x系统Power结构Diagram

Processor working modes and wake - up sources

Table4-4 CPU Mode Table

工作Mode	CPU	外设	SRAM	IO	LPTIM	唤醒源	唤醒时间
Active	Run	Run	可访问	可翻转	Run	-	-
Sleep	Stop	Run	可访问	可翻转	Run	任意中断	<0.5us
DeepSleep	Stop	Stop	不可访问，全保留	电平保持	Run	RTC，唤醒IO，GPIO，LPTIM，蓝牙	250us
Standby	Reset	Reset	不可访问，全保留	电平保持	Run	RTC，唤醒IO，LPTIM，蓝牙	1ms
Hibernate	Reset	Reset	不可访问，不保留	高阻	Reset	RTC，唤醒IO	>2ms

如Table4-5Shown，全系列芯片Support15个Standby和HibernateMode下可唤醒中断源。

Table4-5 Interrupt wake - up source Table

中断源	Pin	DetailedDescription
LWKUP_PIN0	PA24	中断Signal0
LWKUP_PIN1	PA25	中断Signal1
LWKUP_PIN2	PA26	中断Signal2
LWKUP_PIN3	PA27	中断Signal3
LWKUP_PIN10	PA34	中断Signal10
LWKUP_PIN11	PA35	中断Signal11
LWKUP_PIN12	PA36	中断Signal12
LWKUP_PIN13	PA37	中断Signal13
LWKUP_PIN14	PA38	中断Signal14
LWKUP_PIN15	PA39	中断Signal15
LWKUP_PIN16	PA40	中断Signal16
LWKUP_PIN17	PA41	中断Signal17
LWKUP_PIN18	PA42	中断Signal18
LWKUP_PIN19	PA43	中断Signal19
LWKUP_PIN20	PA44	中断Signal20

Clock

芯片需要外部提供2个Clock源，48MHz主Crystal和32.768KHz RTCCrystal，Crystal的具体规格要求和选型As follows：

Important

Table4-6 Crystal specification requirements

Crystal	Crystal specification requirements	DetailedDescription
48MHz	CL≦12pF（推荐值7pF）△F/F0≦±10ppmESR≦30 ohms（推荐值22ohms）	晶振Power consumption和CL,ESR相关,CL和ESR越小Power consumption越低，为了最佳Power consumption性能，Recommend采用推荐值CL≦7pF，ESR≦22 ohms.Crystal旁边Reserve并联MatchingCapacitance,当CL<9pF时，No need焊接Capacitance
32.768KHz	CL≦12.5pF（推荐值7pF）△F/F0≦±20ppm ESR≦80k ohms（推荐值38Kohms）	晶振Power consumption和CL,ESR相关,CL和ESR越小Power consumption越低，为了最佳Power consumption性能，Recommend采用推荐值CL≦9pF，ESR≦40K ohms.Crystal旁边Reserve并联MatchingCapacitance,当CL<12.5pF时，No need焊接Capacitance

Table4-7 Recommended crystal list

Model	Manufacturer	Parameters
E1SB48E001G00E	Hosonic	F0 = 48.000000MHz，△F/F0 = -6 ~ 8 ppm，CL = 8.8 pF，ESR = 22 ohms Max TOPR = -30 ~ 85℃，Package =（2016 公制）
ETST00327000LE	Hosonic	F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm，CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制）
SX20Y048000B31T-8.8	TKD	F0 = 48.000000MHz，△F/F0 = -10 ~ 10 ppm，CL = 8.8 pF，ESR = 40 ohms Max TOPR = -20 ~ 75℃，Package =（2016 公制）
SF32K32768D71T01	TKD	F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm，CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制）

** Note: The ESR of SX20Y048000B31T-8.8 is slightly larger, and the static power consumption will also be slightly higher. When routing the PCB, remove at least the GND copper on the second layer under the crystal to reduce the parasitic load capacitance on the clock signal. **

RF

The RF trace requires a characteristic impedance of 50 ohms.If the antenna is well matched, no additional components need to be added to the RF.It is recommended to reserve a π-type matching network for spurious filtering or antenna matching during design.

Diagram4-7 RFCircuitDiagram

Display

The chip supports 3-Line SPI, 4-Line SPI, Dual data SPI, Quad data SPI, and serial JDI interfaces.Supports 16.7M-colors (RGB888), 262K-colors (RGB666), 65K-colors (RGB565), and 8-color (RGB111) Color depth modes.The maximum supported resolution is 512RGBx512.LCD driverSupportList如Table4-8Shown。

Table4-8 LCD driverSupportList

Model	Manufacturer	Resolution	Type	Interface
RM69090	Raydium	368*448	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，MIPI-DSI
RM69330	Raydium	454*454	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，8-bits 8080-Series MCU ，MIPI-DSI
ILI8688E	ILITEK	368*448	Amoled	Quad data SPI，MIPI-DSI
SH8601A	晟合技术	454*454	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，8-bits 8080-Series MCU ，MIPI-DSI
SPD2012	Solomon	356*400	TFT	Quad data SPI
GC9C01	Galaxycore	360*360	TFT	Quad data SPI
GC9B71	Galaxycore	320*380	TFT	Quad data SPI
ST77903	Sitronix	400*400	TFT	Quad data SPI
ICNA3311	Chipone	454*454	Amoled	Quad data SPI
FT2308	FocalTech	410*494	Amoled	Quad data SPI

SPI/QSPIDisplayInterface

The chip supports 3/4-wire SPI and Quad-SPI interfaces to connect to LCD displays, and the descriptions of each signal are shown in the table below.

Table4-9 SPI/QSPI SignalConnectMethod

spiSignal	Pin	DetailedDescription
CSx	PA03	Enable signal
WRx_SCL	PA04	Clock signal
DCx	PA06	4-wire SPI Mode下的Data/command signalQuad-SPI Mode下的Data1
SDI_RDx	PA05	3/4-wire SPI Mode下的Data input signalQuad-SPI Mode下的Data0
SDO	PA05	3/4-wire SPI Mode下的Data output signal请和SDI_RDX短接到一起
D[0]	PA07	Quad-SPI Mode下的Data2
D[1]	PA08	Quad-SPI Mode下的Data3
RESET	PA00	Reset display signal
TE	PA02	Tearing effect to MCU frame signal

JDIDisplayInterface

The chip supports a parallel JDI interface to connect to LCD displays, as shown in the table below.

Table4-10 ParallelJDI屏SignalConnectMethod

JDISignal	I/O	DetailedDescription
JDI_VCK	PA39	Shift clock for the vertical driver
JDI_VST	PA08	Start signal for the vertical driver
JDI_XRST	PA40	Reset signal for the horizontal and vertical driver
JDI_HCK	PA41	Shift clock for the horizontal driver
JDI_HST	PA06	Start signal for the horizontal driver
JDI_ENB	PA07	Write enable signal for the pixel memory
JDI_R1	PA05	Red image data (odd pixels)
JDI_R2	PA42	Red image data (even pixels)
JDI_G1	PA04	Green image data (odd pixels)
JDI_G2	PA43	Green image data (even pixels)
JDI_B1	PA03	Blue image data (odd pixels)
JDI_B2	PA02	Blue image data (even pixels)

Touch and backlight interface

The chip supports the I2C format touch screen control interface and touch status interrupt input, and also supports a PWM signal to control the enable and brightness of the backlight power supply, as shown in the table below

Table4-11 Touch和Backlight控制ConnectMethod

Touch screen and backlight signals	Pin	DetailedDescription
Interrupt	PA43	Touch status interrupt signal (can wake up)
I2C1_SCL	PA42	Touch screen I2C clock signal
I2C1_SDA	PA41	Touch screen I2C data signal
BL_PWM	PA01	Backlight PWM control signal
Reset	PA44	Touch reset signal

存储

Memory connection interface description

The chip supports four types of external storage media: SPI Nor Flash, SPI NAND Flash, SD NAND Flash, and eMMC

Table4-12 SPI Nor/Nand FlashSignalConnect

Flash Signal	I/OSignal	DetailedDescription
CS#	PA12	片选，低电平有效
SO	PA13	Data Input (Data Input Output 1)
WP#	PA14	写保护输出（数据输入输出2）
SI	PA15	Data Output (Data Input Output 0)
SCLK	PA16	Serial Clock Output
Hold#	PA17	Data Output (Data Input Output 3)

Table4-13 SD Nand Flash和eMMCSignalConnect

Flash Signal	I/OSignal	DetailedDescription
SD2_CMD	PA15	Command signal
SD2_D1	PA17	Data1
SD2_D0	PA16	Data0
SD2_CLK	PA14	Clock signal
SD2_D2	PA12	Data2
SD2_D3	PA13	Data3

Note

The eMMC chip has two power domains, VCC and VCCQ. Method 1: Both power supplies can be controlled together, with low shutdown power consumption, but the eMMC recovers slowly from sleep, resulting in high average CPU power consumption Method 2: VCC can be controlled separately, while VCCQ is always powered on, which results in higher shutdown power consumption than method 1, but the eMMC recovers quickly from sleep, leading to lower average CPU power consumption than method 1

启动设置

The chip supports booting from internally integrated Spi Nor Flash, externally connected Spi Nor Flash, externally connected Spi Nand Flash, and externally connected SD Nand Flash. Among them

• SF32LB520Ux6 has internally integrated flash and boots from the internally integrated flash by default

• SF32LB523/5/7Ux6 has internally integrated psram and must boot from an external storage medium

Diagram4-8 Recommended circuit diagram for Bootstrap pins

Table4-14 Boot option settings

Bootstrap[1] (PA13)	Bootstrap[0] (PA17)	Boot From ext memory
L	L	SPI Nor Flash
L	H	SPI Nand Flash
H	X	SD Nand Flash

启动存储介质Power控制

The chip supports power switch control of the boot storage medium to reduce shutdown power consumption. The enable pin of the power switch must be controlled by PA21, and the enable level of the switch is required to be [high to open, low to close]

Important

• SF32LB520Ux6 has internally integrated flash, please use VDD33_VOUT1 to power VDD18_VOUT, and set the LDO inside VDD18_VOUT to the off state

• SF32LB523/5/7Ux6 has internally integrated psram, using the internal LDO for power supply, VDD18_VOUT can be powered externally

• When the external storage medium is Nor Flash, use VDD33_VOUT1 for power supply, no additional power switch is needed in between

• When the external storage medium is SPI Nand or SD Nand, use VDD33_VOUT1 for power supply, a power switch needs to be added

• In the reference design, pull-up resistor positions are reserved for PA13 and PA17. Choose the pull-up resistor according to the type of storage medium, with a recommended resistance of 7.5K

按键

开关机按键

The chip’s PA34 supports a long press reset function, which can be designed as a button to achieve power on/off + long press reset functionality. The long press reset function of PA34 requires a high level to be effective, so it is designed to be pulled down by default to low, and the level becomes high after the button is pressed, as shown in Figure 4-9

Diagram4-9 Power on/off button circuit diagram

Mechanical knob button

Diagram4-10 Power on/off button circuit diagram

振动马达

The chip supports PWM output to control the vibration motor

Diagram4-11 Vibration motor circuit diagram

音频Interface

芯片的Audio-related interfaces，如Table4-15Shown，音频InterfaceSignal有以下特点：

1. Supports a single-ended ADC input, connecting to an external analog MIC, requiring a DC-blocking capacitor with a capacitance of at least 2.2uF in between, and the power supply of the analog MIC connects to the MIC_BIAS power output pin of the chip

2. Supports a differential DAC output, connecting to an external analog audio PA, the routing of the DAC output should follow differential line routing, ensuring proper ground shielding, and also note that: Trace Capacitor < 10pF, Length < 2cm

Table4-15 音频SignalConnectMethod

音频Signal	Pin	DetailedDescription
BIAS	MIC_BIAS	Microphone power supply
AU_ADC1P	ADCP	Single-ended analog MIC input
AU_DAC1P	DACP	Differential analog output P
AU_DAC1N	DACN	Differential analog output N

The recommended circuit for the analog MEMS MIC is shown in Figure 4-12, and the recommended circuit for the analog ECM MIC single-ended is shown in Figure 4-13, where MEMS_MIC_ADC_IN and ECM_MIC_ADC_IN are connected to the ADCP input pin of SF32LB52x

Diagram4-12 Simulated MEMS MIC single-ended input circuit diagram

Diagram4-13 Simulated ECM single-ended input circuit diagram

The recommended circuit for analog audio output is shown in Figure 4-14. Note that the differential low-pass filter within the dashed box should be placed close to the chip end.

Diagram4-14 Analog audio PA circuit diagram

传感器

The chip supports sensors such as heart rate, acceleration, and geomagnetic sensors.For the power supply of the sensors, a Load Switch with a relatively small Iq should be selected for power switch control.

UART和I2CPin设置

The chip supports arbitrary pin UART and I2C function mapping, and all PA interfaces can be mapped to UART or I2C function pins.

GPTIMPin设置

The chip supports arbitrary pin GPTIM function mapping, and all PA interfaces can be mapped to GPTIM function pins.

调试和下载Interface

The chip supports the DBG_UART interface for downloading and debugging, connecting to the PC via the UART to USB Dongle board at the 3.3V interface.

The SWD interface and DGB_UART interface are multiplexed on PA18 and PA19, and are configured by default as DBG_UART functions upon powering up.

DBG_UART supports single-step debugging and also log output for details, refer to the user manuals of SFtool and Impeller.

Table 4-16 Debug port connection method

DBGSignal	Pin	DetailedDescription
DBG_UART_RXD	PA18	Debug UART 接收
DBG_UART_TXD	PA19	Debug UART 发送

产线烧录和Crystal校准

SiCh provides an offline downloader to complete the burning of production line programs and crystal calibration. When designing the hardware, please ensure to reserve at least the following test points: PVDD, GND, AVDD33, DB_UART_RXD, DB_UART_RXD, PA01.

For detailed programming and crystal calibration, see the “**_Offline Downloader User Guide.pdf” document included in the development materials package.

Schematic and PCB drawing checklist

See the “Schematic checklist.xlsx” and “PCB checklist.xlsx” documents included in the development materials package.

PCB Design Guidelines

PCB封装设计

The QFN68L package size of the SF32LB52x series chip: 7mmX7mmx0.85mm number of pins: 68 PIN pitch: 0.35mm. Detailed尺寸如Diagram5-1Shown。

Diagram5-1 QFN68L package size diagram

Diagram5-2 QFN68L package shape diagram

Diagram5-3 QFN68L package PCB pad design reference diagram

PCB叠层设计

The SF32LB52x series chips support single and double-sided layouts, components can be placed on one side, and capacitors can be placed on the back of the chip.PCBSupportPTH通孔设计，推荐采用4层PTH，推荐参考叠层结构如Diagram5-4Shown。

Diagram5-4 Reference stack structure diagram

PCBGeneral design rules

PTH 板PCBGeneral design rules如Diagram5-5Shown。

Diagram5-5 General design rules

PCBRouting扇出

QFN package signal fan-out, all pins are completely fanned out through the top layer, as shown in Figure 5-6.

如Diagram5-6 Table层扇出参考Diagram

ClockInterfaceRouting

The crystal needs to be placed inside the shield, with a distance greater than 1mm from the PCB frame, and should be kept away from heat-generating components such as PA, Charge, PMU, etc., preferably more than 5mm away to avoid affecting the crystal frequency offset. The prohibited placement area around the crystal circuit should be greater than 0.25mm to avoid other metals and components, as shown in Figure 5-7.

Diagram5-7 Crystal布局Diagram

It is recommended that the 48MHz crystal traces be routed on the surface layer, with length controlled within the 3-10mm range, trace width 0.1mm, must be treated with 3D ground wrapping, and kept away from VBAT, DC/DC, and high-speed signal lines.The area below the 48MHz crystal region and its adjacent layers should be kept clear, prohibiting other traces from passing through its area, as shown in Figures 5-8, 5-9, and 5-10.

Diagram5-8 48MHz crystal schematic diagram

Diagram5-9 48MHz crystal routing model

Diagram5-10 48MHz crystal routing reference

It is recommended that the 32.768KHz crystal traces be routed on the surface layer, with length controlled ≤10mm, trace width 0.1mm.The parallel trace spacing of 32K_XI/32_XO should be ≥0.15mm, and must be treated with 3D ground wrapping.The area below the crystal region and its adjacent layers should be kept clear, prohibiting other traces from passing through its area, as shown in Figures 5-11, 5-12, and 5-13.

Diagram5-11 32.768KHz crystal schematic diagram

Diagram5-12 32.768KHz crystal routing model

Diagram5-13 32.768KHz crystal routing reference

RFInterfaceRouting

RFMatchingCircuit要尽量靠近芯片端放置，不要靠近Antenna端。AVDD_BRFRFPower其FilteringCapacitance尽量靠近芯片Pin放置，Capacitance接地Pin打孔直接接主地。RFSignal的π型Network的原理Diagram和PCB分别如Diagram5-14，5-15Shown。

Diagram5-14 π型Network以及PowerCircuit原理Diagram

Diagram5-15 π型Network以及PowerPCB布局

It is recommended that RF traces be routed on the surface layer to avoid affecting RF performance by drilling through layers. The trace width should be greater than 10mil, and it needs to be processed with a three-dimensional ground wrap, avoiding acute angles and right angles。The RF line is controlled at 50 ohms impedance, with more shielding ground holes punched on both sides，如Diagram5-16, 5-17Shown。

Diagram5-16 RFSignalCircuit原理Diagram

Diagram5-17 RFSignalPCBRoutingDiagram

音频InterfaceRouting

AVDD33_AUD is the power supply pin for audio, its filter capacitor is placed close to the corresponding pin, so that the grounding pin of the filter capacitor can be well connected to the main ground of the PCB。MIC_BIAS is the power output pin for powering the microphone peripheral, its corresponding filter capacitor is placed close to the corresponding pin。同样The filter capacitor of the AUD_VREF pin is also placed close to the pin，如Diagram5-18a，5-18bShown。

Diagram5-18a 音频相关PowerFilteringCircuit

Diagram5-18b 音频相关PowerFilteringCircuitPCB参考Routing

The circuit device corresponding to the ADCP pin for analog signal input should be placed as close to the chip pin as possible, the trace length should be as short as possible, and it should be processed with a three-dimensional ground wrap, away from other strong interference signals，如Diagram5-19a，5-19bShown。

Diagram5-19a 模拟音频Input原理Diagram

Diagram5-19b 模拟音频InputPCB设计

The circuit devices corresponding to the DACP/DACN pins for analog signal output should be placed as close to the chip pins as possible. Each P/N path needs to be routed in differential line form, the routing length should be as short as possible, the parasitic capacitance should be less than 10pf, it needs to be processed with a three-dimensional ground wrap, and kept away from other strong interference signals，如Diagram5-20a，5-20bShown。

Diagram5-20a 模拟音频Output原理Diagram

Diagram5-20b 模拟音频OutputPCB设计

USBInterfaceRouting

The USB traces PA35 (USB DP) / PA36 (USB_DN) must first pass through the ESD device pins, and then to the chip end, ensuring that the ESD device’s ground pin can be well connected to the main ground。The traces need to be routed in differential line form, with 90-ohm differential impedance control, and processed with a three-dimensional package，如Diagram5-21a，5-21bShown。

5-21a USBSignal原理Diagram

5-21b USBSignalPCB设计

Diagram5-22a为USBSignal的元件布局参考Diagram，Diagram5-22b为PCBRouting模型。

Diagram5-22a USBSignalDevice布局参考

Diagram5-22b USBSignalRouting模型

SDIOInterfaceRouting

SDIO signal traces should be routed together as much as possible, avoiding separate routing. The entire trace length ≤50mm, and the intra-group length control ≤6mm。The clock signal of the SDIO interface needs to be processed with a three-dimensional ground wrap, and the DATA and CMD signals also need to be wrapped with ground，如Diagram5-23a，5-23bShown。

Diagram5-23a SDIOInterfaceCircuitDiagram

Diagram5-23b SDIO PCBRouting模型

DCDCCircuitRouting

The power inductor and filter capacitor of the DC-DC circuit must be placed close to the pins of the chip。The BUCK_LX trace should be as short and thick as possible to ensure a small loop inductance for the entire DC-DC circuit；The feedback line of the BUCK_FB pin cannot be too thin, it must be greater than 0.25mm。All DC-DC output filter capacitors have multiple vias connecting their ground pins to the main ground plane。Copper is prohibited on the surface layer of the power inductor area, and the adjacent layer must be a complete reference ground to avoid other lines passing through the inductor area，如Diagram5-24a，5-24bShown。

Diagram5-24a DC-DC关键DeviceCircuitDiagram

Diagram5-24b DC-DC关键DevicePCB布局Diagram

Power供电Routing

VCC is the power input pin of the chip’s built-in PMU module, the corresponding capacitor must be placed close to the pin, and the trace should be as thick as possible, not less than 0.4mm，如Diagram5-25a，5-25bShown。

Diagram5-25a VCCPowerRoutingDiagram

Diagram5-25b VCCPowerRoutingDiagram

The filter capacitors of pins such as VDD_VOUT1, VDD_VOUT2, VDD_RET, VDD_RTC, VDD18_VOUT, VDD33_VOUT1, VDD33_VOUT2, AVDD33_AUD, and AVDD_BRF should be placed close to the corresponding pins. The trace width must meet the input current requirements, and the traces should be as short and thick as possible to reduce power ripple and improve system stability.

Charging circuit routing

VBUS and VBAT are the input and output pins of the built-in charging module of the chip, respectively, and the corresponding filter capacitors need to be placed close to the pins. Since the charging loop current is relatively large, the pin trace width should be at least 0.4mm. Sensitive lines are prohibited from running parallel to avoid interference during charging. Use star routing for traces and do not share routing paths with other traces to avoid interfering with other circuit modules during charging.

Diagram5-26a VBUS&VBATPowerRoutingDiagram

Diagram5-26b VBUS&VBATPowerRoutingDiagram

Other interface routing

For pin configuration as GPADC pin signals, it is necessary to implement three-dimensional ground wrapping and keep away from other interfering signals, such as battery level circuits, temperature check circuits, etc.

EMI&ESD

• Avoid long-distance wiring on the outer surface of the shield, especially for interference signals such as clock and power, which should be routed in the inner layer, and surface routing is prohibited.

• ESD protection devices must be placed close to the corresponding pins of the connector. Signal traces should pass through the ESD protection device pins first to avoid signal branching and bypassing the ESD protection pins.

• The grounding pin of the ESD device must ensure via connection to the main ground, ensuring that the ground pad traces are short and thick to reduce impedance and improve the performance of the ESD device.

其它

The USB charging line test point must be placed in front of the TVS tube, and the battery seat TVS tube is placed in front of the platform. Its wiring must ensure passing through the TVS first and then to the chip end, as shown in Figure 5-27.

Diagram5-27 PowerTVS布局参考

Diagram5-28 TVSRouting参考

The grounding pin of the TVS tube should avoid running a long wire before connecting to the ground, as shown in Figure 5-28.

修订历史

版本	日期	发布说明
0.0.1	10/2024	初始版本