SF32LB56xU-Hardware Design Guide¶

基本介绍¶

The main purpose of this document is to help developers complete the development of watch solutions based on the SF32LB56xU series chip。This article focuses on the precautions related to hardware design during the scheme development process, aiming to minimize the workload of developers and shorten the product’s time to market。

The SF32LB56xU chip is a highly integrated, high-performance system-level (SoC) MCU chip for ultra-low power artificial intelligence Internet of Things (AIoT) scenarios。The chip innovatively adopts a big.LITTLE architecture based on the ARM Core-M33 STAR processor, while integrating the industry’s highest performance 2.5D graphics engine, artificial intelligence neural network accelerator, and low-power Bluetooth 5.3，It can be widely used in various application scenarios such as wristband wearable electronic devices, smart mobile terminals, and smart home。

SF32LB56xUChipProcess器Peripheral资源如下：

44 GPIOs
6x UARTs
7x I2Cs
5x GPTIMs
1x SPI
1x I2S audio interface
1x SDIO storage interface
1x differential analog audio output
1x differential analog audio input
Supports single/dual/quad data line SPI display interface, supports serial JDI mode display interface
Supports two types of display screens with and without GRAM
Supports SWD and UART download and software debugging

封装¶

封装介绍¶

SF32LB56xU的The package information is shown in Table 2-1。

表2-1 封装信息列表

封装名称	尺寸	Pins间距
QFN68L	7x7x0.75 mm	0.35 mm

SF32LB56xU QFN68L封装¶

Figure 2-1 SF32LB56xU QFN68L pin distribution

典型应用方案¶

Figure 3-1 is a block diagram of a typical sports watch composition, the main functions are display, storage, sensors, vibration motor, audio input and output。

../_images/sf32lb56xU-watch-app-diagram.png

Figure3-1 运动手表组成框Figure

Note

Big.LITTLE dual CPU architecture, taking into account both high performance and low power consumption design requirements
External charging management chip
Supports GPADC battery voltage detection function
The power supply adopts Buck, LDO and Load Switch solutions
Supports TFT or AMOLED display with QSPI interface, up to 1024*1024 resolution
Supports PWM backlight control
Supports external Nor Flash memory chip with QSPI interface
Supports external NAND Flash memory chip with QSPI interface
Supports external NAND Flash memory chip with SDIO interface
Supports Bluetooth 5.3 communication
Supports analog audio input
Supports analog audio output
Supports PWM vibration motor control
Supports acceleration/geomagnetic/gyroscope sensors with SPI/I2C interface
Supports heart rate/blood oxygen/electrocardiogram sensors with I2C interface
Supports SEGGER J-Link SWD debugging and burning tools
Supports UART debugging print interface
Supports Bluetooth HCI debugging interface
Supports one-to-many program burning in the production line
Supports crystal calibration function in the production line
Supports OTA online upgrade function

原理Figure设计指导¶

Power¶

The series chip has a built-in PMU unit, PVDD can support power input from 1.71~3.6V。The PMU supports one Buck and multiple LDOs to power the internal circuits of the chip, detailed connection methods for each power pin refer to Table 4-1。

Process器Power supplyRequirement¶

SF32LB56xU power supply specifications：

表4-1 PMU Power supply规格

PMUPower pins	Minimum voltage(V)	典型Voltage(V)	Maximum voltage(V)	Maximum current(mA)	Detailed description
PVDD	1.71	1.8	3.6	100	PVDD power input
BUCK_LX BUCK_FB	-	1.25	-	100	BUCK_LX output, connect to the internal power input of the inductor, connect to the other end of the inductor, and externally connect a capacitor
LDO1_VOUT	-	1.1	-	50	LDO1 output, externally connected capacitor
LDO2_VOUT	-	0.9	-	20	LDO2 output, externally connected capacitor
VDD_RET	-	0.9	-	1	RET LDO output, externally connected capacitor
VDD_RTC	-	1.1	-	1	RTC LDO output, externally connected capacitor
MIC_BIAS	1.4	-	2.8	-	MIC power output
AVDD33_ANA	3.15	3.3	3.45	50	Analog power + RF PA power input
AVDD33_AUD	3.15	3.3	3.45	50	Analog audio power
VDDIO1	1.71	1.8	2.0	-	Internal large core co-packaged memory power input
VDDIO2	1.71	1.8	3.45	-	PA GPIO (except PA5~11) power input
VDDIO3	1.71	1.8	3.45	-	PA5~11 power input
VDDIO4	1.71	1.8	3.45	-	PB GPIO and internal small core co-packaged Flash power input

The recommended values of external capacitors for the power pins of the SF32LB56xU series chips are shown in Table 4-2。

表4-2 CapacitorRecommendation值

Power pins	Capacitor	Detailed description
PVDD	0.1uF + 10uF	靠近Pins的地方至少放置10uF和0.1uF 共2颗Capacitor.
BUCK_LX BUCK_FB	0.1uF + 4.7uF	靠近Pins的地方至少放置4.7uF和0.1uF 共2颗Capacitor.
LDO1_VOUT	4.7uF	Place at least one 4.7uF capacitor close to the pins.
LDO2_VOUT	4.7uF	Place at least one 4.7uF capacitor close to the pins.
VDD_RET	0.47uF	Place at least one 0.47uF capacitor close to the pins.
VDD_RTC	1uF	Place at least one 1uF capacitor close to the pins.
AVDD33_ANA	4.7uF	Place at least one 4.7uF capacitor close to the pins.
AVDD33_AUD	4.7uF	靠近Pins的地方至少放置1颗4.7uF颗Capacitor.
MIC_BIAS	1uF	Place at least one 1uF capacitor close to the pins.
VDDIO1	1uF	Place at least one 1uF capacitor close to the pins.
VDDIO2	1uF	Place at least one 1uF capacitor close to the pins.
VDDIO3	1uF	Place at least one 1uF capacitor close to the pins.
VDDIO4	1uF	Place at least one 1uF capacitor close to the pins.

思澈PMICChipPower分配¶

SF30147C is a highly integrated, high-efficiency, and cost-effective power management chip for ultra-low power wearable products。SF30147C integrates one high-efficiency and low quiescent current BUCK with an output of 1.8V, providing up to 500mA of drive current。SF30147C integrates four low dropout and low quiescent current LDOs with an output of 2.8~3.3V, providing up to 100mA of drive current。

SF30147C integrates seven low quiescent current and low on-resistance load switches。Among them, there are two high-voltage load switches suitable for peripherals directly driven by battery voltage, such as audio amplifiers；Five low-voltage switches are suitable for peripherals powered by 1.8V。

SF32LB56xU can communicate with SF30147C through the TWI interface。SF30147C的各路PowerOutput使用Situation请见表4-3所示，该Chip的详细Situation请Refer to《DS0002-SF30147C-ChipTechnical specification》Document。

表4-3 SF30147CPower分配表

SF30147C Power pins	Minimum voltage(V)	Maximum voltage(V)	Maximum current(mA)	Detailed description
VBUCK	1.8	1.8	500	SF32LB56xU的PVDD，VDDIOA，VDDIOA2，VDDIOB，VDDIOSA，VDDIOSB，VDDIOSC，AVDD_BRF等1.8VPowerInput
LVSW1	1.8	1.8	100	1.8VPower supplyOutput
LVSW2	1.8	1.8	100	G-SENSOR 1.8VPower supplyInput
LVSW3	1.8	1.8	150	心率 1.8VPower supplyInput
LVSW4	1.8	1.8	150	LCD 1.8VPower supplyInput
LVSW5	1.8	1.8	150	1.8VPower supplyOutput
LDO1	2.8	3.3	100	SF32LB56xU的AVDD33_ANA，AVDD33_AUD，VDDIOA2等3.3VPowerInput
LDO2	2.8	3.3	100	MotorPower supplyInput
LDO3	2.8	3.3	100	LCD 3.3VPower supplyInput
LDO4	2.8	3.3	100	心率3.3VPower supplyInput
HVSW1	2.8	5	150	模拟Class-K PAPower supplyInput
HVSW2	2.8	5	150	GPSPower supplyInput

Power-on sequence and reset¶

SF32LB56xUChipPMU内部Integrate了Power on reset(Power on reset)和Brownout reset(Brownout reset)Function，SpecificRequirement如Figure4-1所示。

hardware/assets/56xU/SF32LB56xU-PoweronresetBrownoutreset.png

Figure4-1 上/下电时序Figure

When the system powers on and PVDD rises to 1.5V, the system completes POR；When PVDD drops to the voltage value that triggers BOR (configurable between 2.5V-1.5V), the PMU outputs a reset signal and the system resets。

Typical power circuit¶

It is recommended to use SF30147C to power SF32LB56xU and various peripherals，Circuit diagramReference如Figure4-2所示，SpecificDescriptionRefer to表4-3。

Figure4-2 SF30147CPower supplyFigure

The SF32LB56xU series chips have one built-in BUCK output，如Figure4-3所示。

Figure4-3 Built-inBUCKCircuit diagram

The SF32LB56xU series chips have four built-in LDOs，如Figure4-4所示。

Figure 4-4 Built-in LDO circuit diagram

Requirements for selecting the processor BUCK inductor¶

Important

Key parameters of power inductor

L(inductance value) = 4.7uH ± 20%, DCR(DC resistance) ≦ 0.4 ohm, Isat(saturation current) ≧ 450mA.

Battery and charging control¶

A sports watch generally has a built-in polymer lithium battery pack, and the entire power system needs to add a charging circuit to complete the battery charging.

The typical charging circuit consists of a protection circuit (EOS, ESD and OVP protection), a charging management chip and a battery.The charging management chip in the Figure 4-1 circuit does not have path management function, the system power supply and the battery are hung together, because the leakage power consumption of the VBAT-powered module is too large, it does not meet the power consumption requirements of the Shipping Mode, so it does not support Shipping Mode.

Figure 4-5 Typical charging circuit one

As shown in Figure 4-6, the trickle charge current of the charging management chip must be greater than i1+i2 to achieve the charging of the over-discharged battery. If the trickle charge current is less than i1+i2, it will lead to the inability to charge the over-discharged battery.

Figure 4-6 Schematic diagram of over-discharged battery charging circuit

As shown in Figure 4-7, if the VBAT back-end system is started up and works normally, the constant current charging current of the charging management chip must be greater than i1+i2. If it is less than i1+i2, both the charging management chip and the battery will power the back-end system, resulting in the inability to fully charge the battery.

Figure 4-7 Schematic diagram of the charging management chip with small charging current

In the Figure 4-8 circuit, the charging management chip is a complex chip with path management and can support Shipping Mode. Since VSYS powers the system and charges VBAT separately, even if the battery is over-discharged, it does not affect the power supply to the subsequent system.

Figure 4-8 Typical charging circuit two

How to reduce standby power consumption¶

To meet the long battery life requirement of the watch product, it is recommended to use load switches for dynamic power management of various functional modules in the hardware design if it is a normally-on module or channel, choose appropriate devices to reduce static current. SF32LB56xU整个System需要3.3V和1.8V两种Power来Power supply，其中：

主ChipSF32LB56xU部分Pins常供3.3V和1.8VPower；
外围器件接口电平Recommendation1.8V；
Other各个模块通过Load switch来做PowerSwitch管理，且默认关闭。

As shown in Figures 4-5, 4-6 and 4-7, depending on the selection of peripheral devices, SF32LB56xU has three types of power supply topology methods for low, medium, and high system power consumption.As shown in Figure 4-9, both PVDD and VDDIO1-4 of SF32LB56xU input 1.8V, peripherals select devices with an interface level of 1.8V, compared to the other two power supply topologies, the overall system power consumption is the lowest.As shown in Figure 4-10, the MCU maintains a 1.8V power supply, peripherals select devices with an interface level of 3.3V, the overall system power consumption is increased compared to the method in Figure 4-9.As shown in Figure 4-11, except that the VDDIO1 pin for powering the on-chip PSRAM supplies 1.8V, both peripheral devices and MCU supply 3.3V. Compared with the previous two methods, the overall system power consumption is the highest. Users can choose which power supply topology to adopt based on the selection of devices and system power consumption requirements.

During the design process, it should be noted that the default hardware logic level of the GPIO pin controlling the load switch should be consistent with the enable level of the load switch to ensure that the load switch is closed by default it is recommended to leave a pull-up or pull-down resistor on the enable pin of the load switch, and the recommended resistance value is 1M ohms.

Figure 4-9 SF32LB56xU 1.8V peripheral power topology diagram

../_images/SF32LB56xU-3V3-INTERFACE-1.png

Figure 4-10 SF32LB56xU 3.3V peripheral power topology diagram one

../_images/SF32LB56xU-3V3-INTERFACE-2.png

Figure4-11 SF32LB56xU 3.3VPeripheralPower拓扑Figure二

Reset问题¶

SF32LB56xUChipPMU内部Integrate了Power on reset(Power on reset)和Brownout reset(Brownout reset)Function，SpecificRequirement如Figure4-12所示。

Figure4-12 上/下电时序Figure

启动模式¶

SF32LB56xUSeriesChip提供一个ModePins来Configuration启动模式，内部有下拉，不使用时可悬空，ReferenceCircuit diagram如Figure4-13所示：

Figure4-13 ModePinsRecommendationCircuit diagram

Attention

ModePins定义：

=1，System启动时进入下载模式，不会进入用户程序；

=0，System启动时rom会检查是否存在用户程序，存在就进入用户程序，否则就进入下载模式。

注意事项：

Mode的Voltage域是和VDDIO2同一Voltage域；
ModePins在量产板上Must留测试点，程序下载或校准晶体时要用到，Can不用预留跳线；
ModePins在测试板上建议要预留跳线，程序死机后方便从下载模式启动下载程序。

Process器工作模式及唤醒源¶

SF32LB56xUSeriesChipHCPU和LCPU都支持表4-4中的多种工作模式。

表4-4 CPU工作模式列表

工作模式	CPU	Peripheral	SRAM	IO	LPTIM	唤醒源	唤醒时间
Active	Run	Run	可访问	可翻转	Run
WFI/WFE	Stop	Run	可访问	可翻转	Run	任意中断	< 0.5us
DEEPWFI	Stop	Run	可访问	可翻转	Run	任意中断	< 5us
Light sleep	Stop	Stop	不可访问，全保留	Level maintained	Run	RTC，GPIO，LPTIM, 跨System，蓝牙，比较器	< 100us
Deep sleep	Stop	Stop	不可访问，全保留	Level maintained	Run	< 300us
Standby	Reset	Reset	不可访问， LP全保留，HP只保留160KB	Level maintained	Run	RTC，Press键，LPTIM，跨System，蓝牙	1.5ms+recovery
Hibernate rtc	Reset	Reset	Data not retained	High impedance	Reset	RTC，Press键	> 2ms
Hibernate pin	Reset	Reset	Data not retained	High impedance	Reset	Press键	> 2ms

As shown in Table 4-5, the full range of chips support 8 wake-up interrupt sources that can wake up either the big core or small core CPU.

表4-5 可唤醒中断源列表

中断源	Pins	Detailed description
WKUP_PIN0	PB32	中断Signal0
WKUP_PIN1	PB33	中断Signal1
WKUP_PIN2	PB34	中断Signal2
WKUP_PIN5	PA50	中断Signal5
WKUP_PIN6	PA51	中断Signal6
WKUP_PIN10	PBR0	中断Signal10
WKUP_PIN11	PBR1	中断Signal11
WKUP_PIN12	PBR2	中断Signal12

时钟¶

The SF32LB56xU series chip requires two external clock sources, a 48MHz main crystal and a 32.768KHz RTC crystal. For specific specifications and selection of the crystals, please refer to Tables 4-6 and 4-7.

Important

晶体关键参数

表4-6 晶体规格Requirement

晶体	晶体规格Requirement	Detailed description
48MHz	CL≦12pF（Recommendation值7pF） △F/F0≦±10ppm ESR≦30 ohms（Recommendation值22ohms）	The power consumption of the crystal oscillator is related to CL and ESR the smaller the CL and ESR, the lower the power consumption. For optimal power consumption performance, it is recommended to use the recommended values of CL ≦ 7pF and ESR ≦ 22 ohms. A parallel matching capacitor is reserved next to the crystal. When CL < 9pF, no capacitor needs to be soldered.
32.768KHz	CL≦12.5pF（Recommendation值7pF） △F/F0≦±20ppm ESR≦80k ohms（Recommendation值38Kohms）	晶振功耗和CL,ESR相关,CL和ESR越小功耗越低，为了最佳功耗性能，建议采用Recommendation值CL≦9pF，ESR≦40K ohms. 晶体旁边预留并联匹配Capacitor,当CL<12.5pF时，无需焊接Capacitor.

晶体Recommendation

表4-7 Recommendation晶体列表

型号	厂家	参数
E1SB48E001G00E	Hosonic	F0 = 48.000000MHz，△F/F0 = -6 ~ 8 ppm， CL = 8.8 pF，ESR = 22 ohms Max TOPR = -30 ~ 85℃，Package =（2016 公制）
ETST00327000LE	Hosonic	F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm， CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制）
SX20Y048000B31T-8.8	TKD	F0 = 48.000000MHz，△F/F0 = -10 ~ 10 ppm， CL = 8.8 pF，ESR = 40 ohms Max TOPR = -20 ~ 75℃，Package =（2016 公制）
SF32K32768D71T01	TKD	F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm， CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制）

注：SX20Y048000B31T-8.8的ESR略大，Static功耗也会略大些。

PCB走线时，在晶体下面至少挖掉第二层的GND铜来减少Clock signal上的寄生负载Capacitor。

射频¶

The RF PCB trace requirement for the SF32LB56xU series chip is 50ohms characteristic impedance. If the antenna is well matched, no additional components need to be added to the RF section.It is recommended to reserve a π-type matching network for stray filtering during design.请ReferenceFigure4-14所示电路。

Figure4-14 射频Circuit diagram

大小核Process器如何接Peripheral¶

The SF32LB56xU series chip has two processor systems inside, where the GPIO of PAx is connected to the HCPU system, and the GPIO of PBx is connected to the LCPU system.HCPU can access all peripheral resources of LCPU, but LCPU is not recommended to access the resources of HCPU.HCPU can reach up to 240MHz main frequency, used to provide high-performance computing, graphics processing, and high-resolution/frame-rate display. External memory, display interface, and other high-power devices need to be connected to HCPU.

LCPU normally runs at 48M@0.9V, and can reach up to 96M@1.1V, used to handle BLE protocol stack and control heart rate and acceleration sensors, charging and PMIC management, voltage monitoring, and power on/off management in low-power mode.

显示¶

The SF32LB56xU series chip supports 3-Line SPI, 4-Line SPI, Dual data SPI, Quad data SPI, and serial JDI interfaces.Supports 16.7M-colors (RGB888), 262K-colors (RGB666), 65K-colors (RGB565), and 8-color (RGB111) color depth modes.The maximum supported resolution is 1024RGBx1024.LCD driver支持列表如表4-8所示。

表4-8 LCD driver支持列表

型号	厂家	分辨率	类型	接口
RM69090	Raydium	368*448	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，MIPI-DSI
RM69330	Raydium	454*454	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，8-bits 8080-Series MCU ，MIPI-DSI
ILI8688E	ILITEK	368*448	Amoled	Quad data SPI，MIPI-DSI
SH8601A	Shenghe Technology	454*454	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，8-bits 8080-Series MCU ，MIPI-DSI
SPD2012	Solomon	356*400	TFT	Quad data SPI
GC9C01	Galaxycore	360*360	TFT	Quad data SPI
ST77903	Sitronix	400*400	TFT	Quad data SPI

SPI/QSPI 显示接口¶

The SF32LB56xU series chips support 3/4-wire SPI and Quad-SPI interfaces to connect LCD displays，各Signal描述如表4-9所示。

表4-9 SPI/QSPI屏Signal连接方式

SPISignal	SF32LB56XUPins	SS6700APins	Detailed description
CSX	PA36	PA36	Enable signal
WRX_SCL	PA37	PA37	Clock signal
DCX	PA39	PA39	4-wire SPI 模式下的Data/command signal Quad-SPI 模式下的Data1
SDI_RDX	PA38	PA38	3/4-wire SPI 模式下的Data input signal Quad-SPI 模式下的Data 0
SDO	PA38	PA38	3/4-wire SPI 模式下的Data output signal 请和SDI_RDX短接到一起
D0	PA40	PA40	Quad-SPI 模式下的Data 2
D1	PA41	PA41	Quad-SPI 模式下的Data 3
REST	PA05	PB04	Reset display signal
TE	PA33	PA33	Tearing effect to MCU frame signal

JDI 显示接口¶

The SF32LB56xU series chip supports a serial JDI interface to connect the LCD display，如表4-10所示。

表4-10 串行JDI屏Signal连接方式

JDISignal	Pins	Detailed description
JDI_SCS	PA39	Chip Select Signal
JDI_SCLK	PA41	Serial Clock Signal
JDI_SO	PA40	Serial Data Output Signal
JDI_DISP	PA36	Display ON/OFF Switching Signal
JDI_EXTCOMIN	PA38	COM Inversion Polarity Input

触摸和背光接口¶

The SF32LB56xU series chip supports I2C format touch screen control interface and touch status interrupt input, and simultaneously supports one PWM signal to control backlight power enable and brightness，如表4-11所示。

表4-11 触摸和背光控制连接方式

触摸屏和背光Signal	Pins	Detailed description
Interrupt	PA50	Touch status interrupt signal（可唤醒）
I2C1_SCL	PA48	Touch screen I2C clock signal
I2C1_SDA	PA49	Touch screen I2C data signal
BL_PWM	PA31	Backlight PWM control signal
Reset	PB18	Touch reset signal

存储¶

SF32LB56xU外接存储器¶

SF32LB56xU supports SPI Nor/Nand and SD Nand Flash peripherals，其中SPI Nor/NAND Flash采用MPI接口，SD NAND Flash采用SD接口，这几种类型的FlashChip物理Pins完全兼容。接口定义如表4-12，4-13所示，表中的PA06~PA11这几个GPIOPower supplyPins是VDDIO3，独立于OtherGPIO的Voltage域。Can根据Peripheralflash的接口电平来设定VDDIO3。

MPI的Signal定义如表4-13所示，SD的Signal定义如表4-14所示。

表4-12 SPI Nor/Nand FlashSignal连接

Flash Signal	I/OSignal	Detailed description
CS#	PA06	Chip select, active low.
SO	PA07	Data Input (Data Input Output 1)
WP#	PA08	Write Protect Output (Data Input Output 2)
SI	PA09	Data Output (Data Input Output 0)
SCLK	PA10	Serial Clock Output
Hold#	PA11	Data Output (Data Input Output 3)

Note

SPI NAND Flash的Hold#PinsNeeds to be pulled up to the power supply of the SPI NAND Flash through a 10K resistor。

表4-13 SD Nand FlashSignal连接

Flash Signal	I/OSignal	Detailed description
SD2_CMD	PA09	Command signal
SD2_D1	PA11	Data1
SD2_D0	PA10	Data 0
SD2_CLK	PA08	Clock signal
SD2_D2	PA06	Data 2
SD2_D3	PA07	Data 3

Press键¶

The SF32LB56xU series chip uses PB32 for power on/off signals, allowing the short press power on/off function and long press reset function to be combined into one button。如Figure4-15所示，The design adopts a high-level active mode, and the long-press reset function requires pressing for more than 10 seconds for the chip to automatically reset。

The SF32LB56xU series chip supports functional button input and knob signal input, and the button or knob signal needs to be pulled up。Press键用法如Figure4-16所示。It can also support optical tracking sensors, and it is recommended to use the I2C4 interface，Signal连接如表4-14所示。

表4-14 光追踪传感器Signal连接

I2CSignal	I/O	Detailed description
SDA	PA18	光追踪传感器I2C DataSignal
SCL	PA17	光追踪传感器I2C Clock signal

Figure4-15 Switch机Press键Circuit diagram

Figure4-16 FunctionPress键或旋钮Circuit diagram

Note

For general mechanical rotary encoder switches, the switch cannot return to the off state after rotation, so the power supply connected to the pull-up resistor is required to be turned off during standby to prevent leakage。

振动马达¶

The SF32LB56xU series chip supports multi-channel PWM output, which can be used as the drive signal for the vibration motor。Figure4-17所示为Recommendation电路，If the current when the motor vibrates does not cause system instability, VBAT power supply can also be used directly。

Figure4-17 振动马达电路示意Figure

音频接口¶

The audio-related interfaces of the SF32LB56xU series chip，如表4-15所示，音频接口Signal有Below特点：

Supports one differential ADC input, externally connected to an analog MIC, requiring a DC-blocking capacitor with a capacitance value of at least 2.2uF in between, and the power supply of the analog MIC connects to the MIC_BIAS power output pin of the chip；
Supports one differential DAC output, externally connected to an analog audio PA, the routing of the DAC output should follow differential line routing, ensuring proper ground shielding，还需要注意：Trace Capacitor < 10pF, Length < 2cm。

表4-15 音频Signal连接方式

音频Signal	I/O	Detailed description
AU_ADC1P	ADCP	差分P或单端模拟MICInput
AU_ADC1N	ADCN	差分模拟MICInputN或GND
AU_DAC1P	DACP	差分模拟OutputP
AU_DAC1N	DACN	差分模拟OutputN

SF32LB56xUSeriesChip模拟MEMS MICRecommendation电路如Figure4-18所示，模拟ECM MIC 单端Recommendation电路如Figure4-19所示，模拟ECM MIC 差分Recommendation电路如Figure4-20所示，其中AU_ADC1P，AU_ADC1N是连接到SF32LB56XU的ADCInputPins。

Figure4-18 模拟MEMS MICInputCircuit diagram

Figure4-19 模拟ECM单端InputCircuit diagram

Figure4-20 模拟ECM差分InputCircuit diagram

SF32LB56xUSeriesChip的模拟音频OutputRecommendation电路如Figure4-21所示，注意虚线框内的差分低通滤波器要靠近Chip端放置。

Figure4-21 模拟音频PACircuit diagram

PBR接口Description¶

The SF32LB56xU series chip provides three PBR interfaces，其主要特点：

PBR0 will change from 0 to 1 during startup, used for certain external LSW controls, while PBR1-PBR2 default output is 0；
PBR0-PBR2 can be used as outputs whether in standby or hibernate；
PBR0-PBR2 can output LPTIM signals；
PBR1-PBR2 can output 32K clock signals；
PBR0-PBR2 can be configured as inputs for wake-up signal input when the MCU wakes up, no interrupt is received。

传感器¶

The SF32LB56xU series chip supports heart rate, acceleration sensors, etc.，In the design, attention should be paid to the I2C, SPI, control interfaces, and interrupt wake-up interfaces of the heart rate and acceleration sensors it is recommended to use the PB interface of the LCPU。The power supply for the heart rate and acceleration sensors uses the LVSWx or LDO output of the SF30147C, enabling the power supply to be switched on and off as needed。

UART和I2CPins设置¶

The SF32LB56xU series chip supports arbitrary pin UART and I2C function mapping，All PA interfaces can be mapped to UART or I2C function pins。Except for PB32/33/34 and PBR0/1/2, all IOs of the PB port can be mapped to UART or I2C function pins。

GPTIMPins设置¶

The SF32LB56xU series chip supports arbitrary pin GPTIM function mapping，All PA interfaces can be mapped to GPTIM function pins。Except for PB32/33/34 and PBR0/1/2, all IOs of the PB port can be mapped to GPTIM function pins。

调试和下载接口¶

The SF32LB56xU series chip supports the Arm® standard SWD debugging interface, which can be connected to EDA tools for single-step operation debugging。如Figure4-22所示，When connecting to the SEEGER® J-Link® tool, the power supply of the debugging tool needs to be changed to external interface input, and the SF32LB56xU circuit board powers the J-Link tool。

The SF32LB56xU series has one SWD for debugging information output，Specific请Reference表4-16。

表4-16 调试口连接方式

SWDSignal	Pins	Detailed description
SWCLK	PB15	JLINKClock signal
SWDIO	PB13	JLINKDataSignal

Figure4-22 调试接口Circuit diagram

产线烧录和晶体校准¶

SiCh Technology provides an offline downloader to complete the burning of production line programs and crystal calibration。

During hardware design, please ensure that at least test points are reserved：VBAT、GND、VDDIO2、Mode、SWDIO、SWCLK、RXD4、TXD4，PB20或PB21或PB25。

For detailed programming and crystal calibration, see the “**_Offline Downloader User Guide.pdf” document included in the development materials package。

原理Figure和PCBFigure纸检查列表¶

See the “Schematic checklist.xlsx” and “PCB checklist.xlsx” documents included in the development materials package。

PCB设计指导¶

PCB 封装设计¶

封装尺寸

The SF32LB56xU chip’s QFN68L package has dimensions: 7mmX7mmx0.75；PIN 间距：0.35mm, 详细尺寸如Figure5-1所示。

Figure5-1 QFN68L封装尺寸Figure

Package Shape

Figure5-2 QFN68LPackage ShapeFigure

Pad Design

Figure5-3 QFN68L封装PCBPad DesignReference

Package PINOUT/BALLMAP

The PINOUT information of SF32LB56xU QFN68L package is shown in Figure 5-4.

Figure5-4 SF32LB56xU封装PINOUT信息

PCB Stack-up Design¶

The layout of the SF32LB56xU series chip supports single and double sides. The QFN package PCB supports PTH, and it is recommended to use 4-layer PTH. The recommended reference stack-up structure is shown in Figure 5-5.

Figure5-5 Reference叠层结构Figure

General PCB Design Rules¶

The general design rules for PTH board PCB are shown in Figure 5-6, with units in mm.

Figure5-6 通用设计规则

Chip Trace Fan-out¶

The QFN package fans out all pins through the top layer, as shown in Figure 5-7.

Figure5-7 表层扇出ReferenceFigure

Clock Interface Traces¶

The crystal needs to be placed inside the shield, with a distance greater than 1mm from the PCB frame, and should be kept away from heat-generating components such as PA, Charge, PMU, etc., preferably at a distance greater than 5mm, to avoid affecting the crystal frequency offset. The prohibited placement area for the crystal circuit should be greater than 0.25mm to avoid other metals and components, as shown in Figure 5-8.

Figure5-8 晶体布局Figure

The 48MHz crystal trace is recommended to be on the surface layer with a length controlled between 3-10mm, a line width of 0.075mm, and must be processed with a three-dimensional ground wrap. Its traces need to be kept away from VBAT, DC/DC, and high-speed signal lines. The area below the 48MHz crystal on the surface layer and adjacent layers should be kept clear, prohibiting other traces from passing through its area, as shown in Figures 5-9, 5-10, and 5-11.

Figure5-9 48MHz晶体原理Figure

Figure5-10 48MHz晶体走线模型

Figure5-11 48MHz晶体走线Reference

The 32.768KHz crystal is recommended to be on the surface layer, with a trace length controlled to ≤10mm, a line width of 0.075mm, and a parallel trace spacing of ≥0.15mm for 32K_XI/32_XO. It must be processed with a three-dimensional ground wrap. The area below the crystal on the surface layer and adjacent layers should be kept clear, prohibiting other traces from passing through its area, as shown in Figures 5-12, 5-13, and 5-14.

Figure5-12 32.768KHz晶体原理Figure

Figure5-13 32.768KHz晶体走线模型

Figure5-14 32.768KHz晶体走线Reference

RF Interface Traces¶

The RF matching circuit should be placed as close to the chip end as possible, not near the antenna end. The filtering capacitor of the AVDD_BRF RF power supply should be placed as close to the chip pin as possible, and the capacitor grounding pin should be directly connected to the main ground through a via. The schematic diagram and PCB of the π-type network of the RF signal are shown in Figures 5-15 and 5-16, respectively.

hardware/assets/56xV/sf32lb56xU-SCH-π.png

Figure5-15 π型网络电路原理Figure

hardware/assets/56xV/sf32lb56xU-PCB-π.png

Figure5-16 π型网络PCB布局

It is recommended that the RF line be on the surface layer to avoid vias affecting RF performance. The line width should be greater than 10 mils, and it needs to be processed with a three-dimensional ground wrap. Avoid sharp and right angles, and place more shielding ground vias on both sides of the RF line. The RF line needs to have 50 ohm impedance control, as shown in Figures 5-17 and 5-18.

hardware/assets/56xV/sf32lb56xU-SCH-RF-R.png

Figure5-17 RFSignal电路原理Figure

hardware/assets/56xV/sf32lb56xU-PCB-RF-R.png

Figure5-18 RFSignalPCB走线

Audio Interface Traces¶

AVDD33_AUD is the pin that powers the audio interface. Its filter capacitor should be placed close to its corresponding pin, and the filter capacitor’s ground pin should be well connected to the main ground. Both AVDD33_ANA and AVDD33_AUD power traces need to be wrapped with ground, whether they are far away from large current and strong interference signals. The two power supplies should be routed in a star configuration to avoid TDD noise in the audio, as shown in Figure 5-19.

Figure5-19 音频电路PowerReference走线

MIC_BIAS is the power supply circuit for the microphone of the audio interface. Its corresponding filter capacitor should be placed close to the corresponding pin, and the filter capacitor’s ground pin should be well connected to the main ground. The AUD_VREF filter capacitor should be placed close to the pin, as shown in Figure 5-20.

Figure5-20 音频电路Power滤波电路PCB设计

For ADCP/ADCN analog signal input, the corresponding circuit devices should be placed as close to the corresponding pins as possible，Each P/N needs to be routed in differential line form，The routing length should be as short as possible，The differential pair routing should be surrounded by ground in three dimensions，Strong interference signals from other interfaces should stay away from their routing，如Figure5-21所示。

Figure5-21 模拟音频InputReference走线

DACP/DACN are analog signal outputs, and the corresponding circuit components should be placed as close to the corresponding pins as possible，Each P/N needs to be routed in differential line form，The routing length should be as short as possible，The parasitic capacitance of the trace is less than 10pf, ,差分对走线需做立体包地Process，Strong interference signals from other interfaces should stay away from their routing，如Figure5-22所示。

Figure5-22 模拟音频OutputReference走线

USB 接口走线¶

USB routing must go through the ESD device pin first, then to the chip end，Ensure that the ESD device’s ground PIN is well connected to the main ground，PA17 (USB DP) / PA18 (USB_DN) are routed in the form of differential lines，Controlled by 90 ohm differential impedance, and treated with 3D package，如Figure5-23所示。Figure5-24为USBSignal的元件布局ReferenceFigure和PCB走线模型。

Figure5-23 USBSignalPCB设计

Figure5-24 USBSignal的元件布局ReferenceFigure和USBPCB走线模型

SDIO 接口走线¶

SF32LB56xU provides one SDIO interface，All SDIO signal routings are together, avoid separate routing，The total routing length is ≤50mm, The length control within the group is ≤6mm. The clock signal of the SDIO interface needs to be processed with a 3D ground wrap，DATA and CM signals also need to be processed with ground wrap，如Figure5-25，5-26所示。

Figure5-25 SDIO接口Circuit diagram

Figure5-26 SDIO PCB走线模型

DC-DC 电路走线¶

The power inductor and filter capacitor of the DC-DC circuit must be placed close to the pins of the chip，The BUCK_LX trace should be as short and thick as possible，Ensure that the inductance of the entire DC-DC circuit loop is small，All DC-DC output filter capacitors have multiple vias on the ground pin connecting to the main ground plane；The feedback line of the BUCK_FB pin cannot be too thin, it must be greater than 0.25mm,Copper is prohibited on the surface layer of the power inductor area，The adjacent layer must be a complete reference ground，Avoid other wires routing through the inductor area，如Figure5-27所示。

Figure5-27 DC-DC 关键器件PCB布局Figure

PowerPower supply走线¶

PVDD is the power input pin of the built-in PMU module of the chip，The corresponding capacitor must be placed close to the pin，The trace should be as thick as possible, not less than 0.5mm; PVSS is the grounding pin of the PMU module, which must be connected to the main ground through a via，Avoid floating and affecting the performance of the entire PMU，如Figure5-28所示。

Figure5-28 PVDDInput走线

LDO和 IO PowerInput走线¶

All LDO output and IO power input pin filter capacitors are placed close to the corresponding pins，The width of its routing must meet the input current requirements，The traces should be as short and thick as possible, thereby reducing power ripple and improving system stability；如Figure5-29所示。

Figure5-29 LDO和IOInputPower走线

其它接口走线¶

If the pin is configured as a GPADC pin signal, it must require 3D ground wrapping treatment，Away from other interfering signals, such as battery level circuits, temperature check circuits, etc.。如Figure5-30所示。

PBR0-2 pins can all be configured as clock output pin signal networks，Must require 3D ground wrapping treatment, away from other interfering signals, such as 32K output, etc.，如Figure5-31所示。

EMI&ESD 走线¶

Avoid long-distance routing on the outer surface of the shield，Especially for clock and power interference signals, try to route them on the inner layer, and prohibit routing on the surface layer；ESD protection devices must be placed close to the corresponding pins of the connector，The signal trace goes through the ESD protection device pin first, avoiding signal bifurcation, without going through the ESD protection pin，The ground pin of the ESD device must ensure via connection to the main ground，Ensure that the ground pad routing is short and thick, reduce impedance and improve the performance of the ESD device。

其它¶

The USB charging cable test point must be placed in front of the TVS tube，The battery seat TVS tube is placed in front of the platform, and its wiring must ensure that it goes through the TVS first and then to the chip end，如Figure5-30所示。

Figure5-30 PowerTVS布局Reference

The ground pin of the TVS tube should avoid running a long wire before connecting to the ground，如Figure5-31所示。

Figure5-31 TVS走线Reference

Q&A¶

问题1：为什么在Mode = 1 启动时，有些GPIO的默认状态和SPEC描述不同？

答：Starting with Mode = 1 will enter the download mode, which will change the status of MPI3 related GPIOs of the external Flash。

问题2：为什么焊接电池时可能会造成死机呢？如何避免？

答：Due to the poor grounding of the soldering iron, surge impact may cause the system to crash。Surge and static protection can be added to the battery interface, and good grounding treatment of the soldering iron can avoid these problems。

修订历史¶

版本	日期	发布Description
0.0.1	3/2025	Draft version