Flash Chipid 和TypeConfiguration Guide

1 Quickly generate Flash driver

1.1 Video tutorial

1.1.1 快速开始：

https://www.bilibili.com/video/BV1i3USY8E3S/

1.1.2 The entire practical process of Nand：

https://www.bilibili.com/video/BV1v3USYbEYy/

1.1.3 Video tutorial网盘地址

Files shared by cloud storage：sifli_flash_driver_generate

链接: https://pan.baidu.com/s/11dVuuK5giQqTr1hQqZ4OVQ?pwd=1234 Extraction code: 1234

1.2 UartburnEx.exe tool

1.2.1 Modification of drive Bin or elf

下载最新的Impeller.exe工具，里面包含了Flash驱动生成工具UartburnEx.exe

Fill in the chipid and configuration parameters of Flash，填入到UartburnEx.exe如下界面中，如果在下载时，要Add an IO port或者Power the Flash through the SF30147 power chip，也可以添加

1.2.2 Download with newly generated driver

1.2.3 SDK代码Chipid添加到对应TYPE

The generated bin or elf only provides Flash download，The own code needs to read and write to this Flash，则Need to add the corresponding Chipid in the code，Then compile Bootloader and user code，The own code can run

1.2.3.1 Method of adding Nor Flash

In the flash_table.c file, add the corresponding Chipid under the corresponding Type

1.2.3.2 Method of adding Nand Flash

In the nand_table.c file, add the corresponding Chipid under the corresponding Type

2 Methods to find ChipID

2.1 案例一GSS01GSAX1

Taking GSS01GSAX1-W8NMI0_Rev_1.1.pdf as an example，After opening, search for the general command to read flash id: 9fh，如下图，You can view the timing diagram of reading id with 9fh and the order of output chipid

下面是9fh命令能读到的ID，After SPI sends the 9FH instruction, it outputs 0x52, 0xca, 0x13 after 8 clk dummies，

Corresponding to the chipid table in the nand_table.c file is： {0x52, 0xCA, 0x13, 0x10, 0x8000000}, //GSS01GSAX1_RDID

2.2 案例二DS35X2GBXXX

Dongxin’s 9Fh read chipid，After 8bit clk dummy, there are only 2 byte chipids，The software will still read 3 bytes by default，Chipid usually loops，If you read 3 bytes, the model of 1V8 in the figure below will receive 0xE5, 0xA2, 0XE5,Similarly, if you read 5 bytes, you will receive 0xE5, 0xA2, 0XE5, 0xE5, 0xA2,The software only takes the first 3 bytes as chipid，得到该chipid为： {0xE5, 0xA2, 0XE5, 0x22, 0x10000000}, //DS35M2GBXXX_RDID

2.3 Print Chipid by downloading

Download with Impeller.exe and check the log to see the Chipid，（这里只演示了uart下载获取chipid方法）

如下图：Select the corresponding CPU model, uart/jlink, speed, nor/nand category, and return to the main interface after the corresponding download address is correct

After clicking Burn, check the log generated during the failed download process at Impeller_x.x.x_COMMON\log\channel\20xx_xx_xx\*.txt, the readable Chipid is {0xc8, 0x82, 0xc8, x, 0xxxxxxxxx},

3 ChipID列表解释

3.1 Nor Flash

3.1.1 ID解释

typedef struct FLASH_FULL_CHIP_ID
{
    uint8_t manufacture_id; /* Manufacturer model, the same for the same manufacturer, 0x52 represents United Storage */
    uint8_t memory_type;  /* Differentiate different storage chip models from the same manufacturer */
    uint8_t memory_density; /* Differentiate different storage chip models from the same manufacturer */
uint8_t ext_flags;    //The meaning of 8 bits, currently nor flash only uses bit 0，
// bit 0: For nor flash, if this bit is 1, it indicates that the flash supports DTR (QSPI dual-edge transmission), 0: indicates not supported, after setting this to 1 here, whether the user code adopts the DTR mode is determined by the code
    // bit 1: -  7  No meaning for nor flash, default is 0
    uint32_t mem_size;  // Flash storage size
} FLASH_RDID_TYPE_T;

ID示例说明

{0x85, 0x20, 0x1a, 1, 0x4000000}, //PY25Q512HB_RDID

0x85：Represents Puya company’s chip

0x20：Represents memory type

0x1a：Represents memory device ID

1： Represents support for DTR dual-edge transmission

3.2 Nand Flash

3.2.1 ID解释

typedef struct FLASH_FULL_CHIP_ID

{

uint8_t manufacture_id; /* Manufacturer model, the same for the same manufacturer, 0x52 represents United Storage \*/

uint8_t memory_type; /* Differentiate different storage chip models from the same manufacturer \*/

uint8_t memory_density; /* Differentiate different storage chip models from the same manufacturer \*/

uint8_t ext_flags; //The meaning of 8 bits, currently nand flash only uses bit 1 - bit7，

// bit 0：For Nand flash, this bit has no meaning, this bit needs to be set to 0，

// bit 1: Nand flash plane flag bit, 1: two planes 0: no double plane (common)

// bit 2: Nand flash page size flag bit, 0: commonly defaults each page to 2048 1: each page is 4096

// bit 3: For NAND flash block size flag bit, 0: commonly each block is 64 pages 1: each block is 128 pages

// bit 4~7: For NAND ECC status mode as NAND_ECC_MODE_T, it is the ECC flag bit

uint32_t mem_size; // Flash storage size

} FLASH_RDID_TYPE_T;

ID示例说明

Ext_flags的8个bit的含有，比如：

{0xE5, 0x74, 0xE5, 0x22, 0x20000000}, //DS35X4GMXXX_RDID

0x22的二进制为0b0010 0010

Bit4-7为0b0010，ECC标识位为2，

Bit3为0：每个block为64个page，size为64x2KB=128KB

Bit2为0：每个page为2048个byte

Bit1为1：该Flash有2个plane

Bit0为0 ：无意义

3.2.2 是否使用Plane

NAND FLASH中plane的概念

NAND utilizes a multi-Plane design to enhance performance。如上图，A NAND is divided into two planes, and the blocks within the two planes are numbered in a single-double alternating pattern，并且We can operate on each plane individually to achieve ping-pong operations to improve performance。所以，We introduce the interleave algorithm, which refers to an algorithm that accesses multiple planes under a single channel to improve NAND performance。

3.2.3 Pagesize

The concept of page and block in NAND FLASH

In Nand flash, a page is the smallest unit for reading and writing, and a block is the smallest unit for erasure。Each Nand address can be precise to bytes (address arrangement), but still uses the page as the smallest unit for R/W (read/write), requiring page alignment for operations。

page（Page）：

A page is the smallest programmable unit in NAND Flash memory, typically sized at 2KB, 4KB, or 8KB。

When writing data, the entire page needs to be erased to 0xFF first, then the whole page of data is written；

When reading data, it can be read by page or by byte。

A page is the basic operational unit in NAND Flash memory, and data must be written in integer multiples of pages。

如下图: A page size is 2024(2K) + 64 bytes, with the extra 64 bytes at the end of each page usually used for marking bad blocks and ECC checks

3.2.4 Blocksize

block（Block）：

A block is the smallest erasable unit in NAND Flash memory, typically containing multiple pages。

The block size is typically 64KB, 128KB, or 256KB, and may vary depending on the model of NAND Flash memory。

Erase operations are performed on a block basis, meaning the entire block is erased to all 1s。

Once data is stored in a block, individual pages within that block cannot be written or erased directly the entire block must be erased before new data can be written。

如下图: A block size is 64 pages (totaling 64x2K=128K Bytes)，

参考文章：

NAND Flash memory is typically organized in terms of pages and blocks。以下是 NAND Flash 的page与block结构的简要介绍： 原文链接：https://blog.csdn.net/gqd0757/article/details/140107931

在实际application中，To reduce the number of erase-write cycles of NAND Flash memory and extend its lifespan, embedded file systems (such as UBIFS, JFFS2, FlashDB, etc.) are often used to manage the pages and blocks of NAND Flash memory。Bad block management and these file systems will reasonably allocate and manage data, reducing the impact of erase-write operations on NAND Flash memory。

也可以采用EMMC存储，EMMC storage already includes a Nand read-write controller and Nand flash, with the Nand controller including bad block management and wear leveling operations。

3.2.5 配置ECC参数

3.2.5.1 NAND和ECC概念

NAND is a type of non-volatile memory chip commonly used in flash memory and SSDs (solid-state drives)。Due to its high density and low cost, NAND memory is widely used in various devices。然而，Due to its physical characteristics, NAND memory is prone to issues such as bit flipping and data loss。

ECC (Error Correction Code) is a coding technique used to detect and correct errors in data transmission。By adding redundant information to the data, ECC can help identify and correct errors in data transmission。Common ECC algorithms include Hamming codes and BCH codes, which can detect and correct multiple bit errors。

3.2.5.2 ECC原理

In NAND memory, ECC verification is typically implemented in the memory controller hardware。It is enabled by default. When data is written to the NAND memory, the controller calculates the ECC check code for the data and stores it along with the data。When the data is read, the controller recalculates the ECC check code and compares it with the stored check code。If an error is found, the ECC check code helps the controller identify the erroneous bits and attempts to correct them；

3.2.5.3 ECC状态寄存器

如下图Nand状态寄存器，

Register B0H bit4: The ECC Enable bit is enabled by default，

Register C0H bits 4-6 (some NANDs use 2 bits or 4 bits) are ECC status registers

The data read from the QSPI interface IO is already error-corrected, but to determine if the read data is valid, it is necessary to check the ECC status register of the C0H register.（The ECC status register will be updated after each complete read operation.），If the ECC status register indicates that it exceeds the ECC correctable range, the data needs to be discarded.，但是The bit4-6 indicators of the ECC status register C0H for different NANDs are not the same.，为了适应不同NAND,就需要进行选择。

typedef enum __NAND_ECC_STATUS_MODE_

{

BIT2_IN_C0_T1 = 0, // 有2位状态位, bit 4-5：00： ECC无error; 01：出现1位error但ECC可纠正，其他：提示超过1bit的error且不能被ECC纠正

BIT2_IN_C0_T2 = 1, // There are 2 status bits, bit 4-5: 00: No ECC error, 01 or 11: There is an error but ECC can correct it, 10: There is an error and ECC cannot correct it.

BIT3_IN_C0_T1 = 2, // There are 3 status bits, bit4-6, 000: No error, 001 or 011 or 101 has an error but ECC can correct it, 010: Has more than 8 - bit errors and ECC cannot correct them.

BIT3_IN_C0_T2 = 3, //There are 3 status bits, bit4-6, 000: No error, 111: There is an error and ECC cannot correct it, others: There is an error but ECC can correct it.，

BIT4_IN_C0_T1 = 4, // There are 4 status bits, bit4-7, 0000: No error, xx10: There is an error and ECC cannot correct it, others: There is an error but ECC can correct it.

BIT4_IN_C0_T2 = 5, // There are 4 status bits, bit4-7, 0000: No error, greater than 1000: There is an error and ECC cannot correct it, others: There is an error but ECC can correct it.

BIT2_IN_C0_T3 = 6 // 有2位状态位, bit 4-5：00：ECC无error; 01：出现了1-2位error但ECC可纠正，10：出现了1-2位error但ECC可纠正，11：有error且不能被ECC纠正

} NAND_ECC_MODE_T;

3.2.5.4 ECC配置例1

{0xE5, 0x74, 0xE5, 0x22, 0x20000000}, //DS35X4GMXXX_RDID

如上图，C0H has 3 - bit status bits ECC_S0 - S2, which conforms to description 2 (010 has an error and cannot be corrected), the ECC parameter bit is in ext_flags 0x22, where bit4 - 7 is 2.。

3.2.5.5 ECC配置例2

{0xc8, 0xd9, 0xc8, 0x10, 0x8000000}, //GD5F1GQ4UxxH_RDID

如上图，C0H has 2 - bit status bits ECCS0 - S1 (ECCSE0 - 1 is in the F0H register, the code does not handle this), which conforms to description 1 (10 has an error and cannot be corrected), the ECC parameter bit is in ext_flags 0x10, where bit4 - 7 is 1.。

3.2.5.6 ECC配置例3

{0x0B, 0x11, 0X00, 0x50, 0x8000000}, //XT26G01CXXX_RDID

如上图，C0H has 4 - bit status bits ECCS0 - S3, which conforms to description 5 (greater than 1000: there is an error and cannot be corrected), the ECC parameter bit is in ext_flags 0x50, where bit4 - 7 is 5.。

4 Flash Type选择

4.1 Nor Flash

4.1.1 DTR概念

Flash DTR mode is the abbreviation of Dual Transfer Rate (dual transfer rate), which means that data transmission is triggered on both edges of the clock signal SCK, which can improve transmission efficiency.。DTR mode is similar to Double Data Rate (DDR) mode, both are dual - edge triggered, but DDR usually refers to the data transfer rate, while DTR focuses more on the concept of transfer rate.，

Whether DTR function is supported.

As shown in the figure below, search for EDh. If you can see the following DTR 4 - wire IO read command, it means support.

4.1.2 QE标志位概念

QE bit (Quad Enable bit) is an abbreviation for Quad Enable, an important concept in serial NOR Flash, called four - line enable in Chinese。In serial NOR Flash, QE bit is used to control pin function multiplexing。具体来说，QE bit决定了Pin3和Pin7的功能：When QE bit is enabled, these pins are used for data transmission when QE bit is not enabled, these pins are used for WP# (write protection), HOLD# (hold) and other control functions。

4.1.3 WRSR2寄存器

WRSR2 register is the abbreviation of WRite Status Register 2. The way different Nor read and write WRSR2 registers is divided into two types.，如下：

Type0 没有单独31h来写WRSR2寄存器（少数）

Use the method of writing 01H to write 2 bytes to the WRSR2 register.，如下图

Type1 有单独的31H来写WRSR2寄存器（占大多数）

备注：一部分支持31H命令的Nor也支持01H连续写2个byte的方式operationWRSR2，因此放在Type0或Tpye1都可以；

Datasheet查找方法，搜索31H命令，如果没有31H命令就只能放在Type0，

如下图type0和type1的区别就只有31H命令

如下图BY25Q256FS这颗 01H支持连续写S15-S8（即WRSR2），31H也支持单独写S15-8，放在Type0或Tpye0都可以；

4.1.4 读OTP的地址MODE

TYPE选择中，有提到OTP的命令3byte还是4byte问题，这里做一个简单介绍

Nor通常提供了大约256byte的Security Registers.寄存器（俗称OTP(One Time Program)区），这个区域其实是可以多次擦写的，但是也能配置为OTP保护起来，用于存储安全或者重要信息，比如蓝牙（网络）地址，device名，序列号，支付宝加密等信息，

在大于128Mbit的nor中，读写也有3byte还是4byte的命令差异（程序中对应命令：SPI_FLASH_CMD_RDSCUR ），如下图：

4.1.5 NOR之4字节地址模式

背景

容量低于16MB（128Mbit） bytes的 nor，一般使用 3 字节地址模式，即命令格式是cmd + addr[2] + addr[1] + addr[0] + …

使用超过16M bytes 的 nor flash，则需要 4 字节地址模式， 即命令格式是 cmd + addr[3] + addr[2] + addr[1] + addr[0] + …

原因

为什么呢, 因为用 3 个字节表示地址，则其范围是 0x000000 - 0xffffff = 0 - 16M，超过 16M 的地址就无法表示了，那自然就得上 4 字节了，而4字节就能支持从256Mbit到32Gbit了，

3字节4字节切换问题

超过128Mbit的flash为了兼容原有MCU boot ROM代码，芯片出厂默认是3字节模式(可访问128Mbit内的内容)，然后通过发送B7h命令进入4字节模式，发送E9h也能退出4字节模式。

有无4字节模式命令6Ch

有些nor厂商，并没有6Ch专门的4四节地址命令，在3字节地址模式下，用6Bh，四字节地址下还是用6Bh命令，这样命令就会有差异，TYPE就会不一样，如下

4.1.6 每个TYPE的介绍

typedef enum

{

NOR_TYPE0 = 0, // normal type 0, DTR, NO CMD_WRSR2, Max 128Mb, as default command table

NOR_TYPE1, // type 1, WRSR2 to write status register 2(QE), Max 128Mb

NOR_TYPE2, // type 2, 256Mb, DTR, 4 bytes address command diff with 3 bytes, OTP support 4-B mode

NOR_TYPE3, // type 3, 256Mb , NO DTR , 4 bytes command same to 3 bytes, only timing changed, OTP 3-B only

NOR_TYPE4, // type 4, 256Mb, NO DTR, 4B ADDR command diff with 3B addr , OTP support 4-B mode

NOR_TYPE5, // type 5, 256Mb, NO DTR, MXIC flash have too many diff with others

NOR_CMD_TABLE_CNT

} FLASH_CMD_TABLE_ID_T;

NOR_TYPE0	128Mbit and below, supports DTR, no 31h command to write WRSR2 register
NOR_TYPE1	128Mbit and below, supports DTR, has 31h command to write WRSR2 register
NOR_TYPE2	256Mbit and above, supports DTR, has a separate 6Ch command for 4-byte operation, OTP supports 4Byte address access
NOR_TYPE3	256Mbit and above, does not support DTR, no separate 6Ch command for 4-byte operation, both 3-byte and 4-byte addresses are operated by the 6Bh command, OTP only supports 3Byte address access
NOR_TYPE4	256Mbit and above, does not support DTR, has a separate 6Ch command for 4-byte operation, OTP supports 4Byte address access
NOR_TYPE5	256Mbit and above, does not support DTR, this TYPE of MXIC flash has relatively large differences

4.1.7 TYPE选择流程图

4.2 Nand Flash

4.2.1 QE标志位概念

QE bit (Quad Enable bit) is an abbreviation for Quad Enable, an important concept in serial NOR Flash, called four - line enable in Chinese。In serial NOR Flash, QE bit is used to control pin function multiplexing。具体来说，QE bit决定了Pin3和Pin7的功能：When QE bit is enabled, these pins are used for data transmission when QE bit is not enabled, these pins are used for WP# (write protection), HOLD# (hold) and other control functions**。**

Many NANDs default to only supporting 4 - wire mode and do not have a QE mark bit, so there is no need to switch from single - wire to four - wire，

QE标志位怎么查

Directly search QE in the datasheet, or search for B0h (some NANDs call it Bxh register) feature register to check whether there is a QE flag bit，如下图，就是带QE标志位，请选择带QE标志位的TYPE，如果搜索不到就是不需要QE切换

4.2.2 EBh命令概念

EBh and 6Bh are both fast 4 - wire read commands. The difference is that the page address sent by the EBh command is also a 4 - wire method, which will be faster, but some NANDs do not support it，如下是6Bh命令，可以直接datasheet搜索EBh命令，如果没有，就是不支持

When distinguishing TYPE, we will look at how many dummies are after the EBh instruction，这里介绍如何区分：

4个Dummy方式如下图，在发完16bit的page地址后，紧跟的4个Dummy时钟，

2个Dummy方式如下图：发完16个bit的page地址后只跟了2个dummy时钟

4.2.3 NAND连续的概念

The concept of Nand buff read and continuous read，如下图，这颗支持buffer read和continuous read方式

The concept of Buff read

When reading data from QSPI NAND, it needs to be divided into two steps

The first step is Page Data Read (13h), which reads data from the cell into the data buffer。此时nand会readcelldata，并计算ecc，进行纠错。如果cell中发生了位翻转，那么经过ecc纠错后写到data buffer中的就已经是正确的data了

The second step, Read Data (6Bh or EBh), reads data from the data buffer。

可以看到，data buffer是读写的必经之路。

The concept of continuous read

Buff read can only read one page with one command, to read the next page, the above two steps need to be continued，

这时有些Nand公司推出了连续读，

当BUF=0标志位为0时，device处于Continuous read mode，data输出

将从data buffer的第一个字节开始，并自动递增到下一个更高的地址。当一个page的data buffer读完后，下一个page的第一个字节的data将紧随其后继续输出下一个page的data，直到读完整个NAND。因此可以达到使用单个读指令read整个NAND,

To determine whether continuous read function is supported, you can search for Continuous Read, or check the 6Bh command to see if there is an expression as shown in the figure below, BUF = 1 (this flag bit indicates whether to use the continuous read function)

4.2.4 每个TPYE介绍

typedef enum

{

NAND_TYPE0 = 0, // normal type, base on winbond w25n01gw, with NON-BUF, NO QE, EB with 4 dummy

NAND_TYPE1, // based on XT26G01D, BUF, QE, EB, EB with 2 dummy

NAND_TYPE2, // based on ds35x1gaxxx, BUF , QE, NO EB

NAND_TYPE3, // based on tc58cyg0s3hraij, BUF, NO QE, NO EB

NAND_TYPE4, // based on FM25LS01, BUF, NO QE, EB with 4 dummy

NAND_TYPE5, // based on GD5F1GM7RE, BUF, QE, EB, EB with 4 dummy

NAND_CMD_TABLE_CNT

} NAND_CMD_TABLE_ID_T;

NAND_TYPE0	Supports continuous read mode, no QE flag bit, followed by 4 empty dummy clocks after the EBh command
NAND_TYPE1	With QE flag bit, followed by 2 empty dummy clocks after the EBh command
NAND_TYPE2	With QE flag bit, no EBh command
NAND_TYPE3	No QE flag bit, no EBh command
NAND_TYPE4	无QE标志位，EBh命令后面跟4个空dummy时钟
NAND_TYPE5	带QE标志位，EBh命令后面跟4个空dummy时钟

4.2.5 TYPE选择流程图

5 常见问题

5.1 Flash下载的原理

5.1.1 Uart下载

Through the Uart interface, burn the corresponding Flash bin, such as loading ram_patch_52X_NAND.bin into the specified address in the RAM of the MCU 52, then jump to that RAM address, and then execute the operation code for burning external Nor or Nand Flash。

5.1.2 Jlink下载

When Jlink is connected to the MCU through the SWD interface and executes the command line：

Loadbin d:\1.bin 0x62000000这个命令时，Jlink.exe会从JLinkDevices.xml配置里面根据对应的0x62000000地址，选择Devices/SiFli/SF32LB52X_EXT_NAND2.elf加载到52这颗MCU的RAM中，调用elffile中对应的烧录接口进行烧录。

5.2 Uart下载过程Log分析

5.2.1 ChipID读不到

如下图Download with Impeller.exe and check the log to see the Chipid，（这里只演示了uart下载获取chipid方法），发现Chipid读不到

Common causes:

1. There is no Flash power supply or the power supply voltage does not match, pay special attention to the differences between 1.8V and 3.3V Flash

2. Poor Flash soldering or soldered reversely

3. After the burning fails, if there is no power supply for the Flash after measurement, and the hardware problem is excluded, the common issue is that the power supply for the Flash in the burning driver is not turned on. It is necessary to configure the corresponding way to turn on the Flash power supply in the generation tool（如果供电不是默认供电的话），

5.2.2 烧录BIN没有跑起来

见5.1章节Flash的烧录原理介绍

见下面的打印

16:18:48:151 uart COM19 open success //This prompt indicates that the downloaded serial port 19 was opened successfully，

16:18:54:499 DownLoadUart() fail //This indicates that the BIN file failed to be downloaded to the MCU's RAM via Uart and run successfully

16:18:54:499 FINAL_FAIL 500bf

Common causes:

1. Abnormal power supply of MCU, MCU did not start up

2. The MCU runs in the user program, but the corresponding Uart port or Jlink is not connected or the MCU crashes

Solutions:

Let the MCU enter the Boot mode, and confirm on the serial port that the print of entering the Boot mode is seen

1）For the 55, 56, and 58 series MCUs, there is a dedicated Boot_Mode pin. After pulling it high, the print of entering the boot mode is as follows:

2）For the 52 series chips, there is no dedicated Boot_Mode pin. You can enter the boot mode by inputting commands within 3 seconds after power-on, and the corresponding print is as follows:

5.2.3 Log prompts verification failure

如下的Log

![alt text](./assets/flash41.png)<br>

15:41:28:413 burn_verify 0x622c0000 0x34ecf8 0xa80ad8a1

15:41:28:939 R: burn_verify 0x622c0000 0x34ecf8 0xa80ad8a1

addr:0x622c0000, size:0x1f000000 sector:0x20000 page:0x800 id:0x13501

V: 0xa80ad8a1 vs 0x63bd755c, TIMR:0xff DCR:0x3c00000

Fail

Common reasons

1. Poor soldering of chip D2-D3
   因为readFlash ID只需要D0-D1data线，能读到ID不代表所有IO都接触好，所以在能read到ID但出现check失败时，如果Flash芯片不是SMT机贴的情况下，特别要检查D2-D3是否焊接或者接触正常（常发生在手动焊接或者Flash插座接触不良）
   

2. The QSPI wiring is too long or the flying wires cause interference leading to individual bit errors
   

5.2.4 Uart serial port receives garbled characters

msh >B

19:19:36:961 downloadfile: D:\bin\ec_lb567_weilaijing\ER_IROM1.bin addr: 0x64080000 len: 3459652 Byte

19:19:36:961 burn_erase_write 0x64080000 0x34ca44

19:19:41:670 R: ?&?

19:19:41:671 download_image_simple_thread fail

19:19:41:798 DownLoadUart fail

19:19:41:799 DownLoadUart() fail

19:19:41:808 FINAL_FAIL 500bf

如上图：下载过程RX收到乱码

Common reasons

1）The machine restarts during the download process

5.3 QSPI Flash频率问题

The default Flash read-write QSPI CLK frequency is recommended to be around 60Mhz，有些Nor/Nand规格书上写的支持频率到108Mhz以及以上，频率高，优点是data读写加快，缺点是对PCB走线要求高，也会带来更多的EMI干扰，尤其是SDK代码打开DRT双沿CLK采样后，对走线要求更高。

The method to modify the Flash CLK is usually in the HAL_PreInit function of the bsp_init.c file in the corresponding project，取决于Flash连接的哪个MPI接口，时钟源用的哪个，分频系数为多少，如下，如果要提高，就是把mpi2_div从5改成4，即变成了288Mhz/4 = 72Mhz，修改后，也可以通过串口命令sysinfo来查看CLK时钟变化

HAL_RCC_HCPU_EnableDLL2(288000000);

mpi2_div = 5;

HAL_RCC_HCPU_ClockSelect(RCC_CLK_MOD_FLASH2, RCC_CLK_FLASH_DLL2);

5.4 Nand Page/Block issues

Sections 3.2.2 and 3.2.3 mention the increasing trend of Page and Block sizes in large-capacity Nand，When managing Flash in the APP application, the corresponding Page/Block operation methods should also be considered.