SF32LB56xV-Hardware Design Guide¶

基本介绍¶

The main purpose of this document is to help developers complete the development of watch solutions based on the SF32LB56xV series chip。This article focuses on the precautions related to hardware design during the scheme development process, aiming to minimize the workload of developers and shorten the product’s time to market。

The SF32LB56xV chip is a highly integrated, high-performance system-level (SoC) MCU chip for ultra-low power artificial intelligence Internet of Things (AIoT) scenarios。The chip innovatively adopts a big.LITTLE architecture based on the ARM Core-M33 STAR processor, while integrating the industry’s highest performance 2.5D graphics engine, artificial intelligence neural network accelerator, and low-power Bluetooth 5.3, which can be widely used in various application scenarios such as bracelet wearable electronic devices, smart mobile terminals, and smart home。

SF32LB56xV芯片Deal器外设资源如下：

120 GPIOs
6x UARTs
7x I2Cs
5x GPTIMs
4x SPIs
1x I2S audio interface
2x SDIO storage interfaces
1x differential analog audio output
1x differential analog audio input
Supports single/dual/quad data line SPI display interface, DBI 8080, DPI, and serial/parallel JDI mode display interface
Supports two types of display screens with and without GRAM
Supports SWD and UART download and software debugging

封装¶

封装介绍¶

SF32LB56xV的The package information is shown in Table 2-1。

表2-1 封装信息列表

封装名称	尺寸	Channel脚间距	球直径
WBBGA175	6.5x6.1x0.94 mm	0.4 mm	0.25mm

WBBGA175封装¶

Illustration2-1 SF32LB56xV WBBGA175Channel脚分布

典型应用方案¶

Figure 3-1 is a block diagram of a typical sports watch composition, with main functions including display, storage, sensors, vibration motor, and audio input and output。

../_images/sf32lb56xV-watch-app-diagram.png

Illustration3-1 运动手表组成框Illustration

Note

The dual-core CPU architecture takes into account both high performance and low power consumption design requirements
External charging management chip
Supports GPADC battery voltage detection function
The power supply adopts Buck, LDO, and Load Switch solutions
Supports 3/4-wire SPI, Dual/Quad data SPI, DBI 8080, DPI, and serial/parallel port JDI displays, with a maximum resolution of 1024*1024
Supports PWM backlight control
Supports external QSPI interface Nor Flash memory chips
Supports external QSPI interface NAND Flash memory chips
Supports external SDIO interface NAND Flash memory chips
Supports Bluetooth 5.3 communication
Supports analog audio input
Supports analog audio output
Supports I2S audio interface
Supports PWM vibration motor control
Supports SPI/I2C interface acceleration/geomagnetic/gyroscope sensors
Supports I2C interface heart rate/oxygen saturation/electrocardiogram sensors
Supports SEGGER J-Link SWD debugging and burning tools
Supports UART debugging print interface
Supports Bluetooth HCI debugging interface
Supports one-to-many program burning in production lines
Supports crystal calibration function in production lines
Supports OTA online upgrade function

原理Illustration设计指导¶

电源¶

The series chip has a built-in PMU unit, and PVDD can support power input from 1.71 to 3.6V。The PMU supports one Buck and multiple LDOs to power the internal circuits of the chip, and the detailed connection method of each power pin can be found in Table 4-1。

Deal器供电要求¶

SF32LB56xV power supply specifications：

表4-1 PMU 供电规格

PMU电源Channel脚	最小电压(V)	典型电压(V)	最大电压(V)	最大电流(mA)	详细Detail
PVDD	1.71	1.8	3.6	100	PVDD power input
BUCK_LX BUCK_FB	-	1.25	-	100	BUCK_LX output, connected to the internal power input of the inductor, the other end of the inductor, and an external capacitor
LDO1_VOUT	-	1.1	-	50	LDO1 output, external capacitor
LDO2_VOUT	-	0.9	-	20	LDO2 output, external capacitor
VDD_RET	-	0.9	-	1	RET LDO output, external capacitor
VDD_RTC	-	1.1	-	1	RTC LDO output, external capacitor
MIC_BIAS	1.4	-	2.8	-	MIC power output
AVDD_BRF	1.71	1.8	3.3	1	RF power input
AVDD33_ANA	3.15	3.3	3.45	50	Analog power + RF PA power input
AVDD33_AUD	3.15	3.3	3.45	50	Analog audio power
VDDIOA	1.71	1.8	3.45	-	PA12-PA78 I/O power input
VDDIOA2	1.71	1.8	3.45	-	PA0-PA11 I/O power input
VDDIOB	1.71	1.8	3.45	-	PB I/O power input
VDDIOSA	1.71	1.8	3.45	-	SIPA power input
VDDIOSB	1.71	1.8	3.45	-	SIPB电源输
入
VDDIOSC	1.71	1.8	3.45	-	SIPC power input

The recommended values for external capacitors on the power pins of the SF32LB56xV series chip are shown in Table 4-2。

表4-2 电容推荐值

电源Channel脚	电容	详细Detail
PVDD	0.1uF + 10uF	靠近Channel脚的地方至少放置10uF和0.1uF 共2颗电容.
BUCK_LX BUCK_FB	0.1uF + 4.7uF	靠近Channel脚的地方至少放置4.7uF和0.1uF 共2颗电容.
LDO1_VOUT	4.7uF	Place at least one 4.7uF capacitor close to the pin.
LDO2_VOUT	4.7uF	Place at least one 4.7uF capacitor close to the pin.
VDD_RET	0.47uF	Place at least one 0.47uF capacitor close to the pin.
VDD_RTC	1uF	Place at least one 1uF capacitor close to the pin.
AVDD_BRF	4.7uF	Place at least one 4.7uF capacitor close to the pin.
AVDD33_ANA	4.7uF	Place at least one 4.7uF capacitor close to the pin.
AVDD33_AUD	4.7uF	靠近Channel脚的地方至少放置1颗4.7uF颗电容.
MIC_BIAS	1uF	Place at least one 1uF capacitor close to the pin.
VDDIOA	1uF	Place at least one 1uF capacitor close to the pin.
VDDIOA2	1uF	Place at least one 1uF capacitor close to the pin.
VDDIOB	1uF	Place at least one 1uF capacitor close to the pin.
VDDIOSA	0.1uF	靠近Channel脚的地方至少放置1颗0.1uF电容.
VDDIOSB	0.1uF	靠近Channel脚的地方至少放置1颗0.1uF电容.
VDDIOSC	0.1uF	靠近Channel脚的地方至少放置1颗0.1uF电容.

思澈PMIC芯片电源分配¶

SF30147C is a highly integrated, high-efficiency, and cost-effective power management chip designed for ultra-low power wearable products。SF30147C integrates one high-efficiency and low quiescent current BUCK with an output of 1.8V, providing up to 500mA of drive current。SF30147C integrates four low dropout and low quiescent current LDOs with an output of 2.8~3.3V, providing up to 100mA of drive current。

SF30147C integrates seven low quiescent current and low on-resistance load switches。Among them, there are two high-voltage load switches suitable for peripherals directly driven by battery voltage, such as audio amplifiers；Five low-voltage switches are suitable for peripherals powered by 1.8V。

SF32LB56XV can communicate with SF30147C via the TWI interface。SF30147C的各路电源输出使用情况请见表4-3Indicated，For more details about this chip, please refer to the document “DS0002-SF30147C-Chip Technical Specifications”。

表4-3 SF30147C电源分配表

SF30147C 电源Channel脚	最小电压(V)	最大电压(V)	最大电流(mA)	详细Detail
VBUCK	1.8	1.8	500	SF32LB56xV’s PVDD, VDDIOA, VDDIOA2, VDDIOB, VDDIOSA, VDDIOSB, VDDIOSC, AVDD_BRF and other 1.8V power inputs
LVSW1	1.8	1.8	100	I2S Class-K PA logic power input
LVSW2	1.8	1.8	100	G-SENSOR 1.8V power input
LVSW3	1.8	1.8	150	Heart rate 1.8V power input
LVSW4	1.8	1.8	150	LCD 1.8V power input
LVSW5	1.8	1.8	150	EMMC CORE power input
LDO1	2.8	3.3	100	SF32LB56xV’s AVDD33_ANA, AVDD33_AUD, VDDIOA2 and other 3.3V power inputs
LDO2	2.8	3.3	100	EMMC or SD NAND power input
LDO3	2.8	3.3	100	LCD 3.3V power input
LDO4	2.8	3.3	100	Heart rate 3.3V power input
HVSW1	2.8	5	150	Analog Class-K PA power input
HVSW2	2.8	5	150	GPS power input

上电时序和复位¶

The PMU inside the SF32LB56xV chip integrates POR (Power on Reset) and BOR (Brownout Reset) functions，具体要求如Illustration4-1Indicated。

Illustration4-1 上/下电时序Illustration

The system powers on, PVDD rises to 1.5V, and the system completes POR；When PVDD drops to the voltage value that triggers BOR (configurable between 2.5V-1.5V), the PMU outputs a reset signal and the system resets。

Typical power supply circuit¶

It is recommended to use SF30147C to power SF32LB56xV and various peripherals，电路IllustrationRegard如Illustration4-2Indicated，具体Specify参见表4-1。

Illustration4-2 SF30147C供电Illustration

SF32LB56xV series chips have a built-in BUCK output，如Illustration4-3Indicated。

Illustration4-3 内置BUCK电路Illustration

SF32LB56xV series chips have 4 built-in LDOs，如Illustration4-4Indicated。

Illustration4-4 内置LDO电路Illustration

Requirements for selecting the processor’s BUCK inductor¶

Important

Key parameters of power inductor

L(inductance) = 4.7uH ± 20%, DCR(DC resistance) ≦ 0.4 ohm, Isat(saturation current) ≧ 450mA。

Battery and charging control¶

Sports watches generally have a built-in polymer lithium battery pack，The entire power system needs to add a charging circuit to complete the battery charging。

A typical charging circuit consists of a protection circuit (EOS, ESD, and OVP protection), a charging management chip, and a battery, etc.。The charging management chip in Figure 4-5 does not have path management function, the system power supply is directly connected to the battery VBAT。The cost of this solution is lower, but the disadvantage is that the downstream module cannot be completely disconnected from VBAT, resulting in higher leakage power consumption, and long-term placement can easily cause over-discharge of the battery。

Illustration4-5 典型充电电路一

As shown in Figure 4-6, the trickle charge current of the charging management chip must be greater than i1+i2 to achieve charging of the over-discharged battery. If the trickle charge current is less than i1+i2, it will result in failure to charge the over-discharged battery。

Illustration4-6 过放电池充电电路示意Illustration

The charging management chip in Figure 4-7 has a path management function. Since VSYS powering the system and VBAT charging the battery are separate, even if the battery is over-discharged, it does not affect the power supply to the downstream system。

Illustration4-7 典型充电电路二

Startup mode¶

The SF32LB56xV series chip provides a Mode pin to configure the startup mode, which can be left floating when not in use，Regard电路Illustration如Illustration4-8Indicated：

Illustration4-8 ModeChannel脚推荐电路Illustration

Attention

ModeChannel脚定义：

=1，StructureCommence时进入Download mode，不会进入用户程序； =0，StructureCommence时rom会检查是否存在用户程序，存在就进入用户程序，否则就进入Download mode。

注意事项：

The voltage domain of Mode is the same as the VDDIOA voltage domain；
Connect a 10K resistor from Mode to the power supply or GND to keep the level stable, it cannot be left floating or have toggle interference；
The Mode pin must leave a test point on the mass production board, which will be used when downloading programs or calibrating crystals, no jumper needs to be reserved；
It is recommended to reserve a jumper for the Mode pin on the test board, so that it is convenient to start downloading the program from the download mode after the program crashes。

Processor operating modes and wake-up sources¶

The HCPU and LCPU of the SF32LB56xV series chips support multiple operating modes in Table 4-4。

表4-4 CPU工作Style列表

工作Style	CPU	外设	SRAM	IO	LPTIM	唤醒源	唤醒时间
Active	Run	Run	可访问	可翻转	Run
WFI/WFE	Stop	Run	可访问	可翻转	Run	任意中断	< 0.5us
DEEPWFI	Stop	Run	可访问	可翻转	Run	任意中断	< 5us
Light sleep	Stop	Stop	不可访问，全保留	电平保持	Run	RTC/GPIO/ LPTIM/LPCOMP/ 跨Structure中断/蓝牙	< 100us
Deep sleep	Stop	Stop	不可访问，全保留	电平保持	Run	RTC/GPIO/ LPTIM/LPCOMP/ 跨Structure中断/蓝牙	< 300us
Standby	复位	复位	不可访问，LP全保留，HP只保留160KB	电平保持	Run	RTC/按键/LPTIM/ 跨Structure中断/蓝牙	1.5ms +recovery
Hibernate rtc	复位	复位	Data不保留	高阻	复位	RTC/按键	> 2ms
Hibernate pin	复位	复位	Data不保留	高阻	复位	按键	> 2ms

As shown in Table 4-5, the full series of chips support 14 wake-up interrupt sources, which can wake up the big core or small core CPU。

表4-5 可唤醒中断源列表

中断源	Channel脚	详细Detail
WKUP_PIN0	PB32	中断信号0
WKUP_PIN1	PB33	中断信号1
WKUP_PIN2	PB34	中断信号2
WKUP_PIN3	PB35	中断信号3
WKUP_PIN4	PB36	中断信号4
WKUP_PIN5	PA50	中断信号5
WKUP_PIN6	PA51	中断信号6
WKUP_PIN7	PA52	Interrupt signal 7
WKUP_PIN8	PA53	Interrupt signal 8
WKUP_PIN9	PA54	Interrupt signal 9
WKUP_PIN10	PBR0	Interrupt signal 10
WKUP_PIN11	PBR1	Interrupt signal 11
WKUP_PIN12	PBR2	Interrupt signal 12
WKUP_PIN13	PBR3	Interrupt signal 13

时钟¶

The SF32LB56xV series chip requires two external clock sources, a 48MHz main crystal and a 32.768KHz RTC crystal，For specific specifications and selection of the crystals, please refer to Table 4-6 and Table 4-7。

Important

Key parameters of the crystal

表4-6 晶体规格要求

晶体	晶体规格要求	详细Detail
48MHz	CL≦12pF（推荐值7pF） △F/F0≦±10ppm ESR≦30 ohms（推荐值22ohms）	The power consumption of the crystal oscillator is related to CL and ESR, the smaller the CL and ESR, the lower the power consumption，For best power consumption performance, it is recommended to use the recommended values of CL≦7pF and ESR≦22 ohms. A parallel matching capacitor is reserved next to the crystal, when CL<9pF, no capacitor needs to be soldered.
32.768KHz	CL≦12.5pF（推荐值7pF） △F/F0≦±20ppm ESR≦80k ohms（推荐值38Kohms）	The power consumption of the crystal oscillator is related to CL and ESR, the smaller the CL and ESR, the lower the power consumption，For best power consumption performance, it is recommended to use the recommended values of CL≦9pF and ESR≦40K ohms. A parallel matching capacitor is reserved next to the crystal, when CL<12.5pF, no capacitor needs to be soldered.

Crystal recommendation

表4-7 推荐晶体列表

型号	厂家	参数
E1SB48E001G00E	Hosonic	F0 = 48.000000MHz，△F/F0 = -6 ~ 8 ppm， CL = 8.8 pF，ESR = 22 ohms Max TOPR = -30 ~ 85℃，Package =（2016 公制）
ETST00327000LE	Hosonic	F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm， CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制）
SX20Y048000B31T-8.8	TKD	F0 = 48.000000MHz，△F/F0 = -10 ~ 10 ppm， CL = 8.8 pF，ESR = 40 ohms Max TOPR = -20 ~ 75℃，Package =（2016 公制）
SF32K32768D71T01	TKD	F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm， CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制）

Note: The ESR of SX20Y048000B31T-8.8 is slightly larger, and the static power consumption will also be slightly larger。 When routing the PCB, at least the GND copper on the second layer under the crystal should be removed to reduce the parasitic load capacitance on the clock signal。

射频¶

The RF PCB trace requirement for the SF32LB56xV series chip is 50ohms characteristic impedance，If the antenna is well matched, no additional devices need to be added to the RF。It is recommended to reserve a π-type matching network for stray filtering during design。请RegardIllustration4-9Indicated电路。

Illustration4-9 射频电路Illustration

大小核Deal器如何接外设¶

The SF32LB56xV series chip has two processor systems inside，Among them, the GPIO of PAx is connected to the HCPU system, and the GPIO of PBx is connected to the LCPU system；HCPU can access all peripheral resources of LCPU, but LCPU is not recommended to access HCPU resources。HCPU can run up to 240HMz main frequency, used to provide high-performance computing, graphics processing and high-resolution/frame rate display，External memory, display interface and other high-power devices need to be connected to HCPU。

LCPU normally runs at 48M@0.9V, and can run up to 96M@1.1V，Used to handle the BLE protocol stack and control of heart rate and acceleration sensors in low power mode, charging and PMIC management, voltage monitoring and power on/off management。

显示¶

The SF32LB56xV series chip supports 3-Line SPI, 4-Line SPI, Dual data SPI, Quad data SPI, DBI 8080, DPI and serial/parallel JDI interfaces。Supports 16.7M-colors (RGB888), 262K-colors (RGB666), 65K-colors (RGB565) and 8-color (RGB111) Color depth modes。The maximum resolution supported is 1024RGBx1024。The LCD driver support list is shown in Table 4-8。

表4-8 LCD driver支持列表

型号	厂家	分辨率	类型	Connector
RM69090	Raydium	368*448	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，MIPI-DSI
RM69330	Raydium	454*454	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，8-bits 8080-Series MCU ，MIPI-DSI
ILI8688E	ILITEK	368*448	Amoled	Quad data SPI，MIPI-DSI
SH8601A	晟合技术	454*454	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，8-bits 8080-Series MCU ，MIPI-DSI
SPD2012	Solomon	356*400	TFT	Quad data SPI
GC9C01	Galaxycore	360*360	TFT	Quad data SPI
ST77903	Sitronix	400*400	TFT	Quad data SPI

SPI/QSPI 显示Connector¶

The SF32LB56xV series chip supports 3/4-wire SPI and Quad-SPI interfaces to connect to LCD displays，各信号Detail如表4-9Indicated。

表4-9 SPI/QSPI屏信号Attach方式

SPI信号	I/O	详细Detail
CSX	PA36	Enable signal
WRX_SCL	PA37	Clock signal
DCX	PA39	Data/command signal in 4-wire SPI mode, Data 1 in Quad-SPI mode
SDI_RDX	PA38	Data input signal in 3/4-wire SPI mode, Data 0 in Quad-SPI mode
SDO	PA38	Data output signal in 3/4-wire SPI mode 请和SDI_RDX短接到一起
D[0]	PA40	Data 2 in Quad-SPI mode
D[1]	PA41	Data 3 in Quad-SPI mode
REST	PA43	Reset display signal
TE	PA33	撕裂效果到MCU帧信号

MCU8080显示Connector¶

SF32LB56xV series chips support the MCU8080 interface to connect to LCD displays，如表4-10Indicated。

表4-10 MCU8080屏信号Attach方式

MCU8080信号	I/O	详细Detail
CSX	PA36	片选信号
WRX	PA37	写数据的选通信号
DCX	PA39	显示数据/命令选择
RDX	PA38	读数据的选通信号
D[0]	PA40	数据0
D[1]	PA1	数据1
D[2]	PA28	数据2
D[3]	PA29	数据3
D[4]	PA30	数据4
D[5]	PA31	数据5
D[6]	PA32	数据6
D[7]	PA34	数据7
REST	PA43	复位
TE	PA33	撕裂效果到MCU帧信号

DPI显示Connector¶

SF32LB56xV series chips support DPI interface to connect to LCD displays，如表4-11Indicated。

表4-11 DPI屏信号Attach方式

DPI信号	I/O	详细Detail
CLK	PA45	Clock signal
DE	PA47	Data valid signal
HSYNC	PA44	Row synchronization signal
VSYNC	PA42	Column synchronization signal
SD	PA50	Control to turn off Display
CM	PA51	Switch between Normal Color and Reduced Color Mode
R0	PA14	Pixel signal
R1	PA13	Pixel signal
R2	PA16	Pixel signal
R3	PA15	Pixel signal
R4	PA19	Pixel signal
R5	PA21	Pixel signal
R6	PA23	Pixel signal
R7	PA25	Pixel signal
G0	PA28	Pixel signal
G1	PA30	Pixel signal
G2	PA32	Pixel signal
G3	PA33	Pixel signal
G4	PA34	Pixel signal
G5	PA29	Pixel signal
G6	PA31	Pixel signal
G7	PA35	Pixel signal
B0	PA36	Pixel signal
B1	PA37	Pixel signal
B2	PA38	Pixel signal
B3	PA43	Pixel signal
B4	PA41	Pixel signal
B5	PA39	Pixel signal
B6	PA40	Pixel signal
B7	PA46	Pixel signal

JDI 显示Connector¶

SF32LB56xV series chips support parallel and serial JDI interfaces to connect to LCD displays，并行JDI如表4-12Indicated，串行JDI如表4-13Indicated。

表4-12 并行JDI屏信号Attach方式

JDI信号	I/O	详细Detail
JDI_VCK	PA41	Shift clock for the vertical driver
JDI_VST	PA40	Start signal for the vertical driver
JDI_XRST	PA39	复位 signal for the horizontal and vertical driver
JDI_HCK	PA36	Shift clock for the horizontal driver
JDI_HST	PA38	Start signal for the horizontal driver
JDI_ENB	PA43	Write enable signal for the pixel memory
JDI_R1	PA29	Red image data (odd pixels)
JDI_R2	PA31	Red image data (even pixels)
JDI_G1	PA34	Green image data (odd pixels)
JDI_G2	PA32	Green image data (even pixels)
JDI_B1	PA30	Blue image data (odd pixels)
JDI_B2	PA28	Blue image data (even pixels)
JDI_XFRP	PBR1	Liquid crystal driving signal (“On” pixel)
JDI_VCOM/FRP	PBR2	Common electrode driving signal/ Liquid crystal driving signal (“Off” pixel)

表4-13 Serial JDI screen signal connection method

JDI信号	Channel脚	详细Detail
JDI_SCS	PA39	Chip Select Signal
JDI_SCLK	PA41	Serial Clock Signal
JDI_SO	PA40	Serial Data Output Signal
JDI_DISP	PA36	Display ON/OFF Switching Signal
JDI_EXTCOMIN	PA38	COM Inversion Polarity Input

触摸和背光Connector¶

SF32LB56xV系列芯片支持I2C格式的触摸屏控制Connector和触摸Stance中断输入，同时支持1路PWM信号来控制背光电源的使能和亮度，如表4-14Indicated。

表4-14 Touch and backlight control connection method

触摸屏和背光信号	Channel脚	详细Detail
Interrupt	PA50	Touch status interrupt signal (can wake up)
I2C1_SCL	PA48	Touch screen I2C clock signal
I2C1_SDA	PA49	Touch screen I2C data signal
BL_PWM	PA35	Backlight PWM control signal
复位	PA44	Touch reset signal

存储¶

SF32LB56xV external memory¶

SF32LB56xV支持SPI Nor/Nand、SD Nand Flash和eMMC外设，其中SPI Nor/NAND Flash采用MPIConnector，SD NAND Flash采用SDConnector，这几种类型的flash芯片物理Channel脚完全兼容。Connector定义如表4-15，4-16Indicated，表中的PA06~PA11这几个GPIO供电Channel脚是VDDIOA2，独立于其他GPIO的电压域。

MPI的信号定义如表4-15Indicated，SD的信号定义如表4-16Indicated，eMMC的信号定义如表4-17Indicated。

表4-15 SPI Nor/Nand Flash signal connection

Flash 信号	I/O信号	详细Detail
CS#	PA06	Chip select, active low.
SO	PA07	Data Input (Data Input Output 1)
WP#	PA08	Write Protect Output (Data Input Output 2)
SI	PA09	Data Output (Data Input Output 0)
SCLK	PA10	Serial Clock Output
Hold#	PA11	Data Output (Data Input Output 3)

Note

SPI NAND Flash的Hold#Channel脚需要通过10K电阻上拉到SPI NAND Flash的供电电源。

表4-16 SD Nand Flash signal connection

Flash 信号	I/O信号	详细Detail
SD2_CMD	PA09	Command signal
SD2_D1	PA11	Data1
SD2_D0	PA10	Data0
SD2_CLK	PA08	Clock signal
SD2_D2	PA06	Data2
SD2_D3	PA07	Data3

表4-17 eMMC signal connection

eMMC 信号	I/O信号	详细Detail
SD1_CMD	PA27	Command signal
SD1_CLK	PA26	Clock signal
SD1_D0	PA22	Data0
SD1_D1	PA15	Data1
SD1_D2	PA12	Data6
SD1_D3	PA20	Data3
SD1_D4	PA21	Data4
SD1_D5	PA19	Data 5
SD1_D6	PA13	Data6
SD1_D7	PA14	Data7

按键¶

The PB32 of SF32LB56xV series chip supports long press reset function, it is recommended to design PB32 as a button, which supports short press power on/off function and long press reset function at the same time。As shown in Figure 4-10, the design adopts the high level effective method. The long press reset function requires to press for more than 10 seconds, then the chip will automatically reset。

SF32LB56xV series chips support function key input and knob signal input, key or knob signals need to be pulled up。按键用法如Illustration4-11Indicated。It also supports light tracking sensor, it is recommended to use I2C4 interface，信号Attach如表4-18Indicated。

表4-18 光追踪传感器信号Attach

I2C信号	I/O	详细Detail
SDA	PA18	光追踪传感器I2C Data信号
SCL	PA17	光追踪传感器I2C Clock signal

Illustration4-10 开关机按键电路Illustration

Illustration4-11 功能按键或旋钮电路Illustration

Note

For general mechanical rotary encoder switches, the switch can’t return to the off state after rotation, so the power supply connected to the pull-up resistor is required to be turned off in standby mode to prevent leakage。

振动马达¶

SF32LB56xV series chips support multi-channel PWM output, which can be used as the driving signal of the vibration motor。Illustration4-12Indicated为推荐电路，If the current when the motor vibrates does not cause system instability, VBAT power supply can also be used directly。

Illustration4-12 振动马达电路示意Illustration

音频Connector¶

SF32LB56xV系列芯片的音频CorrelatedConnector，如表4-19Indicated，音频Connector信号有以下特点：

Supports one differential ADC input, externally connected to an analog MIC, a DC blocking capacitor with a capacitance value of at least 2.2uF needs to be added in between, the power supply of the analog MIC connects to the MIC_BIAS power output pin of the chip；
Supports one differential DAC output, externally connected to an analog audio PA, the routing of the DAC output should follow the differential line routing, ensuring good ground shielding treatment，Also, note that: Trace Capacitor < 10pF, Length < 2cm。

表4-19 音频信号Attach方式

音频信号	I/O	详细Detail
AU_ADC1P	ADCP	差分P或单端模拟MIC输入
AU_ADC1N	ADCN	差分模拟MIC输入N或GND
AU_DAC1P	DACP	差分模拟输出P
AU_DAC1N	DACN	差分模拟输出N
I2S1_LRCK	PA71	I2S2帧时钟
I2S1_SDI	PA69	I2S2Data输入
I2S1_SDO	PA64	I2S2Data输出
I2S1_BCK	PA73	I2S2位时钟

The recommended circuit for the analog MEMS MIC of the SF32LB56xV series chip is shown in Figure 4-13, the recommended circuit for the single-ended analog ECM MIC is shown in Figure 4-14, and the recommended circuit for the differential analog ECM MIC is shown in Figure 4-15，Where AU_ADC1P and AU_ADC1N are connected to the ADC input pins of the SF32LB56xV。

Illustration4-13 模拟MEMS MIC输入电路Illustration

Illustration4-14 模拟ECM单端输入电路Illustration

Illustration4-15 模拟ECM差分输入电路Illustration

The recommended circuit for the analog audio output of the SF32LB56xV series chip is shown in Figure 4-16, note that the differential low-pass filter within the dashed box should be placed close to the chip end 。

Illustration4-16 模拟音频PA电路Illustration

The connection diagram of the I2S audio PA is shown in Figure 4-17, using I2C3 to configure the registers of the I2S audio PA。

Illustration4-17 I2S音频PA电路Illustration

PBRConnectorSpecify¶

The SF32LB56xV series chip provides four PBR interfaces, with the main features：

PBR0 will change from 0 to 1 during startup, used for some external LSW control, while PBR1-PBR3 default output is 0；
PBR0-PBR3 can be used as outputs whether in standby or hibernate mode；
PBR0-PBR3 can output LPTIM signals；
PBR1-PBR3 can output 32K clock signals；
PBR0-PBR3 can be configured as inputs, used for wake-up signal input, when the MCU wakes up, no interrupts are received。

传感器¶

The SF32LB56xV series chip supports heart rate, acceleration sensors, etc., in the design, attention should be paid to the I2C, SPI, control interface, interrupt wake-up and other interfaces of the heart rate and acceleration sensors, it is recommended to use the PB interface of LCPU。The power supply for the heart rate and acceleration sensors uses the LVSWx or LDO output of SF30147C, allowing the power supply to be switched on or off as needed。

UART和I2CChannel脚设置¶

The SF32LB56xV series chip supports arbitrary pin UART and I2C function mapping, all PA interfaces can be mapped to UART or I2C function pins。Except for PB32~36 and PBR0~3, all IOs of the PB port can be mapped to UART or I2C function pins。

GPTIMChannel脚设置¶

The SF32LB56xV series chip supports arbitrary pin GPTIM function mapping, all PA interfaces can be mapped to GPTIM function pins。Except for PB32~36 and PBR0~3, all IOs of the PB port can be mapped to GPTIM function pins。

调试和下载Connector¶

The SF32LB56xV series chip supports the Arm® standard SWD debugging interface, which can be connected to EDA tools for single-step operation debugging。如Illustration4-18Indicated，AttachSEEGER® J-Link® 工具时需要把调试工具的电源修改为外置Connector输入，通过SF32LB56xV电路板给J-Link工具供电。

SF32LB56xV系列有1路SWD进行调试信息输出，具体请Regard表4-20。

表4-20 调试口Attach方式

SWD信号	Channel脚	详细Detail
SWCLK	PB15	JLINKClock signal
SWDIO	PB13	JLINKData信号

Illustration4-18 调试Connector电路Illustration

产线烧录和晶体校准¶

思澈科技提供脱机下载器来完成产线程序的烧录和晶体校准。

硬件设计时，请注意至少预留测试点：VBAT、GND、VDDIOB、Mode、SWDIO、SWCLK、RXD4、TXD4，PB20或PB21或PB25。

详细的烧录和晶体校准见“**_脱机下载器使用指南.pdf”文档，包含在开发资料包中。

原理Illustration和PCBIllustration纸检查列表¶

See the “Schematic checklist.xlsx” and “PCB checklist.xlsx” documents, included in the development materials package.

PCB设计指导¶

PCB 封装设计¶

封装尺寸

The SF32LB56xV chip uses WBBGA packaging, with dimensions: 6.5mm x 6.1mm x 0.94mm, number of pins: 175 ball pitch: 0.4mm, detailed dimensions are shown in Figure 5-1.

Figure 5-1 WBBGA package size diagram

封装形状

Figure 5-2 WBBGA package shape diagram

焊盘设计

Figure 5-3 Reference for WBBGA package PCB pad design

封装PINOUT/BALLMAP

The PINOUT information for the SF32LB56xV’s WBBGA package is shown in Figure 5-4.

Figure 5-4 SF32LB56xV package PINOUT information

封装基板

Figure 5-5 Package substrate BALL information

PCB 叠层设计¶

The SF32LB56xV series chip layout supports single and double-sided placement, PCB does not support PTH boards, only HDI boards are supported, recommended reference stack-up is shown in Figure 5-6.

Figure 5-6 Reference stack-up structure diagram

PCB通用设计规则¶

General design rules for HDI board PCBs are shown in Figure 5-7, units in mm.

Figure 5-7 General design rules

盲孔设计¶

PCB blind hole design is shown in Figure 5-8, units in mm.

Figure 5-8 Blind hole design

埋孔设计¶

PCB buried hole design is shown in Figure 5-9, units in mm.

Figure 5-9 Buried hole design

芯片走线扇出¶

The first two rows of balls in the WBBGA package array use surface fan-out method, as shown in Figure 5-10, other balls use inner layer fan-out method, as shown in Figure 5-11

Figure 5-10 Surface fan-out reference diagram

Figure 5-11 Inner layer fan-out reference diagram

时钟Connector走线¶

The crystal needs to be placed inside the shield, with a distance greater than 1mm from the PCB frame, try to stay away from heat-generating components such as PA, Charge, and PMU circuits, the distance should preferably be more than 5mm to avoid affecting the crystal frequency deviation, the crystal circuit prohibited area spacing is greater than 0.25mm to avoid other metals and devices, as shown in Figure 5-12.

Figure 5-12 Crystal layout diagram

The 48MHz crystal trace is recommended to be on the surface with length controlled within 3-10mm, line width 0.075mm, must be processed with three-dimensional ground wrapping, and its trace needs to be kept away from VBAT, DC/DC and high-speed signal lines. The area below the 48MHz crystal on the surface and adjacent layers should be kept clear, prohibiting other traces from passing through its area, as shown in Figures 5-13, 5-14, 5-15.

Figure 5-13 48MHz crystal schematic diagram

Figure 5-14 48MHz crystal trace model

Figure 5-15 48MHz crystal trace reference

The 32.768KHz crystal is recommended to be on the surface, trace length controlled ≤10mm, line width 0.075mm, 32K_XI/32_XO parallel trace spacing ≥0.15mm, must be processed with three-dimensional ground wrapping, the area below the crystal on the surface and adjacent layers should be kept clear, prohibiting other traces from passing through its area, as shown in Figures 5-16, 5-17, 5-18.

Figure 5-16 32.768KHz crystal schematic diagram

Figure 5-17 32.768KHz crystal trace model

Figure 5-18 32.768KHz crystal trace reference

射频Connector走线¶

The RF matching circuit should be placed as close to the chip end as possible, not near the antenna end, the filtering capacitor of AVDD_BRF RF power supply should be placed as close to the chip pin as possible, the capacitor grounding PIN is directly connected to the main ground via a hole, the schematic diagram and PCB of the π-type network of the RF signal are shown in Figures 5-19 and 5-20 respectively.

Figure 5-19 Schematic diagram of π-type network and power circuit

Figure 5-

射频线建议走表层，Shun打孔穿层影响RF 性能，线宽最好大于10mil，需要立体包地Deal，Shun走锐角和直角，射频线两边多打屏蔽地孔，射频线需做50欧阻抗控制，如Illustration5-21, 5-22Indicated。

Illustration5-21 RF信号电路原理Illustration

Illustration5-22 RF信号PCB走线

RF circuit routing prohibits DC-DC, VBAT and high-speed digital signals from passing through its area, such as crystals, high-frequency clocks, and digital interface signals（I2C,SPI,SDIO,I2S，UART等）。

AVSS_RRF, AVSS_TRF, AVSS_TRF2, AVSS_BB are the grounding pins for the RF circuit, and it must be ensured that they are well grounded，It is recommended to directly blind holes on its pad and connect to the main ground，如Illustration5-23Indicated。

Illustration5-23 射频电路EarthRegard走线

Audio interface routing¶

AVDD33_AUD is the pin that powers the audio interface, and its filter capacitor is placed close to its corresponding pin，The filter capacitor’s ground pin is well connected to the main ground，MIC_BIAS is the power supply circuit for the microphone of the audio interface, and its corresponding filter capacitor is placed near the corresponding pin，The filter capacitor’s ground pin is well connected to the main groundAUD_VREF滤波电容靠近Channel脚放置，如Illustration5-24Indicated。

Illustration5-24 音频电路电源Regard走线

ADCP/ADCN为Analog signal input，The corresponding circuit components should be placed as close as possible to the corresponding pins，Each P/N needs to be routed in differential line form，The trace length should be as short as possible，The differential pair traces are processed with a three-dimensional ground wrap，Strong interference signals from other interfaces should stay away from their wiring，如Illustration5-25Indicated。

Illustration5-25 模拟音频输入Regard走线

DACP/DACN为Analog signal output，The corresponding circuit components should be placed as close as possible to the corresponding pins，Each P/N needs to be routed in differential line form，The trace length should be as short as possible，走线寄生电容小于10pf, ,差分对走线需做立体包地Deal，Strong interference signals from other interfaces should stay away from their wiring，如Illustration5-26Indicated。

Illustration5-26 模拟音频输入Regard走线

USB interface routing¶

USB routing must first pass through the ESD device pin, then to the chip end，Ensure that the ESD device’s ground PIN is well connected to the main ground。PA17(USB DP)/PA18(USB_DN) Routed in differential line form，Controlled by 90 ohm differential impedance and processed with a three-dimensional package，如Illustration5-27Indicated。Illustration5-28为Reference diagram for USB signal component layout and PCB routing model。

Illustration5-27 USB信号PCB设计

Illustration5-28 USB信号的元件布局RegardIllustration和USBPCB走线模型

SDIO interface routing¶

SF32LB56xV 支持2个SDIOConnector，即SDIO1和SDIO2。All SDIO signal routings are together, avoid separate routing，The entire trace length ≤50mm, within-group length control ≤6mm. The SDIO interface clock signal needs to be processed with a three-dimensional ground wrap，DATA and CM signals also need to be wrapped around the ground，如Illustration5-29a，5-29bIndicated。

Illustration5-29a SDIOConnector电路Illustration

Illustration5-29b SDIO PCB走线模型

DC-DC 电路走线¶

The DC-DC circuit power inductor and filter capacitor must be placed close to the chip’s pins，BUCK_LX routing should be as short and thick as possible，Ensure that the entire DC-DC circuit loop inductance is small，All DC-DC output filter capacitors have multiple vias connecting the ground pins to the main ground plane；The BUCK_FB pin feedback line cannot be too thin, it must be greater than 0.25mm,Copper laying is prohibited on the surface layer of the power inductor area，The adjacent layer must be a complete reference ground，Avoid other lines routing through the inductor area，如Illustration5-30Indicated。

Illustration5-30 DC-DC 关键器件PCB布局Illustration

Power supply routing¶

PVDD is the power input pin of the chip’s built-in PMU module, and the corresponding capacitor must be placed close to the pin，The trace should be as thick as possible, not less than 0.5mm; PVSS is the grounding pin of the PMU module, which must be connected to the main ground through a via，Avoid floating and affecting the performance of the entire PMU，如Illustration5-31Indicated。

Illustration5-31 PVDD输入走线

LDO and IO power input routing¶

All LDO outputs and IO power input pin filter capacitors are placed close to the corresponding pins，The width of its routing must meet the input current requirements，The routing should be as short and thick as possible, thereby reducing power ripple and improving system stability；如Illustration5-32Indicated。

Illustration5-32 LDO和IO输入电源走线

其它Connector走线¶

The pin configuration is GPADC pin signal, which must require three-dimensional ground wrapping treatment，Away from other interfering signals, such as battery level circuits, temperature check circuits, etc.。

PBR0~3 pins can all be configured as clock output pin signal networks, which must require three-dimensional ground wrapping treatment，Away from other interfering signals, such as 32K output, etc.。

SF32LB56xV芯片地走线¶

The ground network in the central area of the SF32LB56xV chip needs to be fully connected with traces，Ensure sufficient ground plane and connect to the main ground plane through blind buried vias。如Illustration5-33a、5-33bIndicated。

Illustration5-33a 芯片下1-2层地信号

Illustration5-33b 芯片下3-4层地信号

EMI&ESD routing¶

Avoid long-distance routing on the outer surface of the shield, especially for clock and power interference signals, try to route them on the inner layer, and prohibit routing on the surface layer；ESD protection devices must be placed close to the corresponding pins of the connector，The signal routing first passes through the ESD protection device pin, avoiding signal bifurcation, without passing through the ESD protection pin，The ESD device’s ground pin must ensure via connection to the main ground，Ensure that the ground pad routing is short and thick, reduce impedance and improve ESD device performance。

其它¶

The USB charging cable test point must be placed in front of the TVS tube，电池座TVS Channel 放置在平台前面其走线必须保证先过TVS 然后再到芯片端，如Illustration5-34Indicated。

Illustration5-34 电源TVS布局Regard

The ground pin of the TVS tube should avoid running a long wire before connecting to the ground，As shown in Figure 5-35。

Illustration5-35 TVS routing reference

Q&A¶

Question 1: Why are the default states of some GPIOs different from the SPEC description when Mode=1 starts?

Answer: Starting in Mode=1 enters the download mode, which will change the state of MPI3 related GPIOs of the external Flash.

Question 2: Why may welding the battery cause a crash? How to avoid it?

Answer: Due to the poor grounding of the soldering iron, surge impact may cause the system to crash.Adding surge and electrostatic protection on the battery interface and ensuring good grounding of the soldering iron can avoid these problems.

Revision history¶

Form	Period	Release notes
0.0.1	9/2022	Draft version