SF32LB58x-Hardware Design Guide

基本介绍

The main purpose of this document is to help hardware engineers complete the design of schematics and PCB based on the SF32LB58x series chip。

SF32LB58x is a series of highly integrated, high-performance system-level (SoC) MCU chips for ultra-low power artificial intelligence Internet of Things (AIoT) scenarios。The processor in the chip can well balance the high computing performance during human-computer interaction with the ultra-low operating and sleep power consumption during long standby。It can be widely used in various application scenarios such as wristband wearable electronic devices, smart mobile terminals, and smart home。

The chip integrates a world-class low-power Bluetooth 5.3 transceiver with high reception sensitivity, high transmission power, and low power consumption。

The chip provides rich internal and external storage resources。The fully encapsulated chip has multiple QSPI memory interfaces and SD/eMMC interfaces。And for different models, the chip’s internal SIP has different capacities of NorFlash and PSRAM combinations。

In order to better support display applications, the chip provides a full range of display screen interfaces，These include MIPI-DSI, 3/4-wire SPI, Dual/Quad data SPI, DBI 8080, DPI, parallel/serial JDI, etc。

Schematic diagramDesign指导

Power supply

The SF32LB58x series chip has a built-in PMU power unit, which supports two BUCK outputs, requiring an external inductor and capacitor to return to the power input inside the chip。There are also three internal LDO power supplies that require capacitors to be connected outside the chip。The design of the SF32LB58x watch solution can be externally equipped with the PMIC chip SF30147C from Sich Technology, which not only provides power for the SF32LB58x but also provides power for related peripherals。

思澈PMICChipPower supply分配

SF30147C is a highly integrated, high-efficiency, and cost-effective power management chip for ultra-low power wearable products。SF30147C integrates four LDOs, each with a wide input and output voltage range, and can provide a maximum load current of 100mA。SF30147C integrates seven low-leakage, low on-resistance load switches for different peripherals：2个高压负载Switch，适用于电池Voltage直接驱动的外设，如Audio功放等；5个低压Switch，适用于1.8V供电的外设。SF32LB58x uses two GPIO interfaces to simulate TWI signals to achieve control of SF30147C。SF30147C的各路Power OutputUsageSituation请见Table2.1所示，该Chip的DetailedSituation请Refer to《DS0002-SF30147C-Chip技术Specification书》文档。

Table2.1 SF30147CPower supply分配Table

SF30147C Power Pin	Minimum Voltage(V)	Maximum Voltage(V)	Maximum Current(mA)	Detailed Description
VBUCK	1.8	1.8	500	SF32LB58x的PVDD1，PVDD2，VDDIOA，VDDIOA2，VDDIOB，AVDD_BRF，AVDD18_DSI等1.8VPower supply
LVSW1	1.8	1.8	100	I2S Class-K PA逻辑供电
LVSW2	1.8	1.8	100	G-SENSOR 1.8V供电
LVSW3	1.8	1.8	150	心率 1.8V供电
LVSW4	1.8	1.8	150	LCD 1.8V供电
LVSW5	1.8	1.8	150	EMMC CORE供电
LDO1	2.8	3.3	100	SF32LB58x的AVDD33_USB，AVDD33_ANA，AVDD33_AUD，AVDDIOA2等3.3VPower supply
LDO2	2.8	3.3	100	EMMC或SD NAND供电
LDO3	2.8	3.3	100	LCD 3.3V供电
LDO4	2.8	3.3	100	心率3.3V供电
HVSW1	2.8	5	150	AnalogClass-K PA供电
HVSW2	2.8	5	150	GPS供电

SF32LB58x供电Requirement

The internal integration PMU power supply specifications of the SF32LB58x series chip are shown in Table 2.2。

Table2.2 PMU供电Specification

PMUPower supply 管脚	Minimum Voltage(V)	Typical Voltage(V)	Maximum Voltage(V)	Maximum Current(mA)	Detailed Description
PVDD1	1.71	1.8	3.6	100	PVDD1 power input
PVDD2	1.71	1.8	3.6	50	PVDD2 power input
BUCK1_LX BUCK1_FB	-	1.25	-	100	BUCK1_LX output, connect to inductor internal power input 1, connect to the other end of the inductor, and connect an external capacitor
BUCK2_LX BUCK2_FB	-	0.9	-	50	BUCK2_LX output, connect to inductor internal power input 2, connect to the other end of the inductor, and connect an external capacitor
LDO_VOUT1	-	1.1	-	100	LDO output, external capacitor
VDD_RET	-	0.9	-	1	RET LDO output, external capacitor
VDD_RTC	-	1.1	-	1	RTC LDO output, external capacitor
MIC_BIAS	1.4	-	2.8	-	MIC power output

The power supply specifications for other externally powered SF32LB58x series chips are shown in Table 2.3.

Table2.3 OtherPower supply供电Specification

Other Power Pins	Minimum Voltage(V)	Typical Voltage(V)	Maximum Voltage(V)	Maximum Current(mA)	Detailed Description
AVDD_BRF	1.71	1.8	3.3	1	RF power input
AVDD18_DSI	1.71	1.8	2.5	20	MIPI DSIPower Input 不用请悬空
AVDD33_ANA	3.15	3.3	3.45	50	Analog power + RF PA power input
AVDD33_AUD	3.15	3.3	3.45	50	Analog audio power input
AVDD33_USB	3.15	3.3	3.45	50	USB power input
VDDIOA	1.71	1.8	3.45	-	PA12-PA93 I/O power input
VDDIOA2	1.71	1.8	3.45	-	PA0-PA11 I/O power input
VDDIOB	1.71	1.8	3.45	-	PB I/O power input
VDDIOSA	1.71	1.8	2.5	-	SIPA power input
VDDIOSB	1.71	1.8	2.5	-	SIPB power input
VDDIOSC	1.71	1.8	2.5	-	SIPC power input

The recommended values of external capacitors for the power pins of the SF32LB58x series chip are shown in Table 2.4

Table2.4 CapacitorRecommended Value

Power Pin	Capacitor	Detailed Description
PVDD1	0.1uF + 10uF	Near the Pin的地方At LeastPlace10uF和0.1uF 共2颗Capacitor.
PVDD2	0.1uF + 10uF	Near the Pin的地方At LeastPlace10uF和0.1uF 共2颗Capacitor.
BUCK1_LX BUCK1_FB	0.1uF + 4.7uF	Near the Pin的地方At LeastPlace4.7uF和0.1uF 共2颗Capacitor.
BUCK2_LX BUCK2_FB	0.1uF + 4.7uF	Near the Pin的地方At LeastPlace4.7uF和0.1uF 共2颗Capacitor.
LDO_VOUT1	4.7uF	Place at least one 4.7uF capacitor near the pin.
VDD_RET	0.47uF	Place at least one 0.47uF capacitor near the pin.
VDD_RTC	0.1uF	Place at least one 0.1uF capacitor near the pin.
AVDD_BRF	1uF	Place at least one 1uF capacitor near the pin.
AVDD18_DSI	4.7uF	Place at least one 4.7uF capacitor near the pin.
AVDD33_ANA	1uF	Place at least one 1uF capacitor near the pin.
AVDD33_AUD	4.7uF	Near the Pin的地方At LeastPlace1颗4.7uF颗Capacitor.
AVDD33_USB	1uF	Place at least one 1uF capacitor near the pin.
MIC_BIAS	1uF	Place at least one 1uF capacitor near the pin.
VDDIOA	1uF	Place at least one 1uF capacitor near the pin.
VDDIOA2	1uF	Place at least one 1uF capacitor near the pin.
VDDIOB	1uF	Place at least one 1uF capacitor near the pin.
VDDIOSA	1uF	Place at least one 1uF capacitor near the pin.
VDDIOSB	1uF	Place at least one 1uF capacitor near the pin.
VDDIOSC	1uF	Place at least one 1uF capacitor near the pin.

Power-on Timing and Reset

The SF32LB58x series chip has internal POR (Power On Reset) and BOR (Brownout Reset) functions, and also supports the external hardware reset signal RSTN, with specific requirements as shown in Figure 2.1.

Figure2.1 上/Power OffTiming Diagram

The RSTN reset signal of the SF32LB58x series chip needs to be pulled up to the input voltage domain of PVDD1, and a 0.1uF capacitor should be connected to ground to create an RC delay reset, as shown in Figure 2.2.

Figure2.2 ResetCircuit Diagram

Typical Power Circuit

The SF32LB58x series chip can use the PMIC SF30147C from Sich Technology to provide various power supplies, with each output situation shown in Figure 2.3, and specific usage details can be found in Table 2.1.

Figure2.3 SF30147CPower Supply Diagram

The SF32LB58x series chip package has 2 built-in BUCK outputs, as shown in Figure 2.4.

Figure2.4 内置DCDCCircuit Diagram

Requirements for selecting BUCK inductance

Important

功率电感关键参数

L(inductance value) = 4.7uH, DCR(DC resistance) ≦ 0.4 ohm, Isat(saturation current) ≧ 500mA

The SF32LB58x series chip package has 3 built-in LDO outputs, as shown in Figure 2.5.

Figure2.5 内置LDOCircuit Diagram

Startup mode

The SF32LB58x series chip provides a Mode pin to configure the startup mode, as shown in Table 2.5.

Table2.5 Mode模式Description

ModeConfiguration	Detailed Description
高	After the chip is powered on, it enters the download mode
低	After the chip is powered on, it jumps to the user program area to start

Note

Note事项：

1. The voltage domain of Mode is the same as that of VDDIOA

2. Mode is connected to a 10K resistor to the power supply or GND to keep the level stable, it cannot be left floating and there should be no toggle interference

3. The Mode pin must leave a test point on the mass production board, which will be used when downloading the program or calibrating the crystal, and there is no need to reserve a jumper

4. It is recommended to reserve a jumper for the Mode pin on the test board, so that it is convenient to start downloading the program from the download mode after the program crashes.

Clock

The SF32LB58x series chip requires two external clock sources, a 48MHz main crystal and a 32.768KHz RTC crystal, with specific requirements as shown in Table 2.6.

Table2.6 CrystalSpecificationRequirement

Clock管脚	CrystalSpecificationRequirement	Detailed Description
XTAL48M_XO XTAL48M_XI	Connection到48MHz的基频Crystal。 CrystalRequirement： CL≦12pF（Recommended Value7pF） △F/F0≦±10ppm ESR≦30 ohms（Recommended Value22ohms）	The power consumption of the crystal oscillator is related to CL and ESR, the smaller the CL and ESR, the lower the power consumption. For optimal power consumption performance, it is recommended to use the recommended values of CL≦7pF and ESR≦22 ohms. A parallel matching capacitor is reserved next to the crystal, when CL<9pF, no capacitor needs to be soldered.
XTAL32K_XO XTAL32K_XI	Connection到32.768KHz的基频Crystal。 CrystalRequirement： CL≦12.5pF（Recommended Value7pF） △F/F0≦±20ppm ESR≦80k ohms（Recommended Value38Kohms）	The power consumption of the crystal oscillator is related to CL and ESR, the smaller the CL and ESR, the lower the power consumption. For optimal power consumption performance, it is recommended to use the recommended values of CL≦9pF and ESR≦40K ohms.
AVSS	Connected to ground	Drill to the main ground plane

Crystal recommendation

Table2.7 已认证Crystal型号

型号	厂家	参数
E1SB48E001G00E	Hosonic	F0 = 48.000000MHz，△F/F0 = -6 ~ 8 ppm， CL = 8.8 pF，ESR = 22 ohms Max TOPR = -30 ~ 85℃，Package =（2016 公制）
ETST00327000LE	Hosonic	F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm， CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制）
SX20Y048000B31T-8.8	TKD	F0 = 48.000000MHz，△F/F0 = -10 ~ 10 ppm， CL = 8.8 pF，ESR = 40 ohms Max TOPR = -20 ~ 75℃，Package =（2016 公制）
SF32K32768D71T01	TKD	F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm， CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制）

Note

The ESR of SX20Y048000B31T-8.8 is slightly larger, and the static power consumption will also be slightly larger.

When routing the PCB, at least the GND copper on the second layer under the crystal should be removed to reduce the parasitic load capacitance on the clock signal.

RF

The RF of the SF32LB58x series chip itself adopts on-chip integrated broadband matching filtering technology, and it only needs to ensure that the RF PCB trace has a characteristic impedance of 50ohms.It is recommended to reserve a π-type matching network for stray filtering and antenna matching during design. Please refer to the circuit shown in Figure 2.6.

Figure2.6 RFCircuit Diagram

Note

Note：

The parameter values of the matching network components need to be determined by testing according to the actual antenna and PCB layout.

External memory interface

The SF32LB58x series chip supports connecting Nor FLASH and SPI Nand FLASH through MPI3 or MPI4 interfaces SD NAND and EMMC are connected externally via the SD1 interface.

QSPI Nand Flash interface

The EVB verification board of the SF32LB58x series chip uses ‘MPI4’ to connect to the SPI NAND Flash device by default, please see Table 2.8 for the signals used, and refer to Figure 2.7 for the specific circuit.

Figure2.7 SPI Nand FlashConnectionReferenceCircuit

Table2.8 MPI4SignalConnection

Flash Signal	I/OSignal（MPI4）	Detailed Description
CS#	PA10	Chip select, active low.
SO	PA04	Data Input (Data Input Output 1)
WP#	PA01	Write Protect Output (Data Input Output 2)
SI	PA05	Data Output (Data Input Output 0)
SCLK	PA09	Serial Clock Output
Hold#	PA06	Data Output (Data Input Output 3)

Note

Note：

1. If the production line needs to download the program to the external FLASH, it is necessary to set the PA43 pin of the external FLASH power control high in the download tool software to turn on the external FLASH power supply。

2. The Hold# pin of the SPI NAND Flash needs to be pulled up to the power supply of the SPI NAND Flash through a 10K resistor。

SDIO eMMC/Micro SDInterface

The SF32LB58x series chip supports two SDIO interfaces. By default, SD1 of the EVB board is connected to EMMC or SD NAND, and SD2 is connected to an SD card or WIFI chip，请ReferenceFigure2.8，2.9，2.10所示Circuit。

The SD1 interface uses a total of 12 GPIOs from PA00-PA11, the power domain is VDDIOA2, which supports 1.8V and 3.3V power supply, and the input voltage can be set according to the interface level of the peripheral。It is recommended that SPI NAND FLASH and EMMC use 1.8V interface level。Because the SD NAND FLASH chip only supports 3.3V interface level, VDDIOA2 should be connected to 3.3V voltage。

Figure2.8 EMMCConnectionReferenceCircuit

Figure2.9 SD NANDConnectionReferenceCircuit

Figure2.10 SD卡ConnectionReferenceCircuit

SF32LB58x series chip的SD1,SD2SignalConnection如Table2.9，2.10所示。

Table2.9 SD1SignalConnection

SD1 Signal	I/OSignal	Detailed Description
SD1_D7	PA00	Data7
SD1_D2	PA01	Data6
SD1_D5	PA03	Data 5
SD1_D1	PA04	Data1
SD1_D0	PA05	Data0
SD1_D3	PA06	Data3
SD1_D4	PA07	Data4
SD1_D6	PA08	Data6
SD1_CLK	PA09	Clock signal
SD1_CMD	PA10	Command signal

Table2.10 SD2SignalConnection

SD2 Signal	I/OSignal	Detailed Description
SD2_CMD	PA70	Command signal
SD2_D1	PA75	Data1
SD2_D0	PA76	Data0
SD2_CLK	PA77	Clock signal
SD2_D2	PA79	Data2
SD2_D3	PA81	Data3

Display

MIPI DSI DisplayInterface

SF32LB58x series chipSupport2 lane的MIPI DSIDisplayInterface，如Table2.11所示。

Table2.11 MIPI-DSI SignalConnection

MIPI DSI signal	I/O	Description
CLKP	DSI_CLKP	MIPI Clock signal+
CLKN	DSI_CLKN	MIPI Clock signal-
D0P	DSI_D0P	MIPI Data通道0+
D0N	DSI_D0N	MIPI Data通道0-
D1P	DSI_D1P	MIPI Data通道1+
D1N	DSI_D1N	MIPI Data通道1-
-	AVDD18_DSI	MIPI power input
-	DSI_REXT	Externally connect a 10K resistor to ground
-	AVSS_DSI	Grounding
TE	PB2	撕裂效果到MCU帧信号
RESET	PB5	Reset display signal

SPI/QSPI DisplayInterface

SF32LB58x series chipSupport 3/4-wire SPI和Quad-SPI Interface来ConnectionLCDDisplay屏，大核UsagePA的LCDC1，小核UsagePB的LCDC2，如Table2.12所示。

Table2.12 SPI/QSPI SignalConnectionMethod

SPISignal	I/O（LCDC1）	I/O（LCDC2）	Detailed Description
CSX	PA44	PB08	Enable signal
WRX_SCL	PA46	PB10	Clock signal
DCX	PA48	PB03	4-wire SPI 模式下的Data/command signal Quad-SPI 模式下的Data1
SDI_RDX	PA50	PB09	3/4-wire SPI 模式下的Data input signal Quad-SPI 模式下的Data0
SDO	PA50	PB09	3/4-wire SPI 模式下的Data output signal 请和SDI_RDX短接到一起
D[0]	PA47	PB04	Quad-SPI 模式下的Data2
D[1]	PA45	PB06	Quad-SPI 模式下的Data3
REST	PA74	PB05	Reset display signal
TE	PA43	PB02	撕裂效果到MCU帧信号

MCU8080 DisplayInterface

The SF32LB58x series chip supports the MCU8080 interface to connect to the LCD display，如Table2.13所示。

Table2.13 MCU8080 屏SignalConnectionMethod

MCU8080Signal	I/O	Detailed Description
CSX	PA44	片选
WRX	PA46	Writes strobe signal to write data
DCX	PA48	Display data / command selection
RDX	PA50	Reads strobe signal to write data
D[0]	PA47	Data 0
D[1]	PA45	Data 1
D[2]	PA26	Data 2
D[3]	PA27	Data 3
D[4]	PA42	Data 4
D[5]	PA51	Data 5
D[6]	PA52	Data 6
D[7]	PA58	Data 7
REST	PA24	复位
TE	PA43	撕裂效果到MCU帧信号

DPIDisplayInterface

The SF32LB58x series chip supports the DPI interface to connect to the LCD display，如Table2.14所示。

Table2.14 DPI屏SignalConnectionMethod

DPISignal	I/O	Detailed Description
CLK	PA12	Clock signal
DE	PA13	Data enable signal
HSYNC	PA14	Line synchronization signal
VSYNC	PA15	Column synchronization signal
SD	PA18	Control to turn off Display
CM	PA19	切换Normal Color还是Reduce Color Mode
R0	PA22	Pixel signal
R1	PA23	Pixel signal
R2	PA24	Pixel signal
R3	PA25	Pixel signal
R4	PA26	Pixel signal
R5	PA27	Pixel signal
R6	PA43	Pixel signal
R7	PA44	Pixel signal
G0	PA45	Pixel signal
G1	PA46	Pixel signal
G2	PA47	Pixel signal
G3	PA48	Pixel signal
G4	PA50	Pixel signal
G5	PA53	Pixel signal
G6	PA54	Pixel signal
G7	PA55	Pixel signal
B0	PA56	Pixel signal
B1	PA57	Pixel signal
B2	PA58	Pixel signal
B3	PA61	Pixel signal
B4	PA62	Pixel signal
B5	PA63	Pixel signal
B6	PA65	Pixel signal
B7	PA67	Pixel signal

JDIDisplayInterface

The SF32LB58x series chip supports parallel and serial JDI interfaces to connect to the LCD display，SupportPA的LCDC1或PB的LCDC2复用相应的Signal，It is recommended to use LCDC2 of the PB interface，如Table2.15，Table2.16所示。

Table2.15 并RowJDI屏SignalConnectionMethod

JDISignal	I/O（LCDC1）	I/O（LCDC2）	Detailed Description
JDI_VCK	PA19	PB15	垂直驱动器的移位时钟
JDI_VST	PA22	PB19	垂直驱动器的启动信号
JDI_XRST	PA25	PB16	复位 signal for the horizontal and vertical driver
JDI_HCK	PA43	PB05	Shift clock for the horizontal driver
JDI_HST	PA44	PB10	Start signal for the horizontal driver
JDI_ENB	PA45	PB12	Write enable signal for the pixel memory
JDI_R1	PA46	PB09	Red image data (odd pixels)
JDI_R2	PA47	PB06	Red image data (even pixels)
JDI_G1	PA48	PB08	Green image data (odd pixels)
JDI_G2	PA50	PB04	Green image data (even pixels)
JDI_B1	PA65	PB02	Blue image data (odd pixels)
JDI_B2	PA67	PB03	Blue image data (even pixels)
JDI_XFRP	PBR1	PBR1	Liquid crystal driving signal (“On” pixel)
JDI_VCOM/FRP	PBR2	PBR2	Common electrode driving signal/ Liquid crystal driving signal (“Off” pixel)

Table 2.16 Connection method of serial JDI screen signals

JDISignal	I/O（LCDC1）	I/O （LCDC2）	Detailed Description
JDI_SCS	PA82	PB03	Chip Select Signal
JDI_SCLK	PA84	PB02	Serial Clock Signal
JDI_SO	PA86	PB06	Serial Data Output Signal
JDI_DISP	PA90	PB04	Display ON/OFF Switching Signal
JDI_EXTCOMIN	PA91	PB05	COM Inversion Polarity Input

Touch and backlight interface

SF32LB58x series chipSupports I2C format touch screen control interface and touch status interrupt input，At the same time, it supports one PWM signal to control the enable and brightness of the backlight power chip，如Table2.17所示。

Table 2.17 Connection method for touch and backlight control

Touch屏和BacklightSignal	I/O	Detailed Description
Interrupt	PA69	Touch status interrupt signal (can wake up)
I2C1_SCL	PA17	Clock signal for touch screen I2C
I2C1_SDA	PA16	Data signal for touch screen I2C
BL_PWM	PB44	Backlight PWM control signal
复位	PA15	Touch reset signal
Power Enable	PA12	Touch screen power enable signal

Debug and download interface

SF32LB58x series chipSupportArm® standard SWD debug interface，Can be connected to EDA tools for single-step operation debugging。如Figure2.11所示，When connecting to SEEGER® J-Link® tool, the power supply of the debugging tool needs to be changed to external interface input，Power the J-Link tool through the SF32LB58x circuit board。

SF32LB58xThere are 1 SWD and 6 UART interfaces available for selection for debugging information output，For details, please refer to Table 2.18。

Table 2.18 Debug port connection method

UARTSignal	I/O	Detailed Description
TXD1	PA31	UART1 RXD signal, HCPU default print port
RXD1	PA32	UART1 TXD signal, HCPU default print port
TXD2	PA28	UART2 RXD signal
RXD2	PA29	UART2 TXD signal
TXD3	PA21	UART3 RXD signal
RXD3	PA20	UART3 TXD signal
TXD4	PB37	UART4 RXD signal, LCPU default print port
RXD4	PB36	UART4 TXD signal, LCPU default print port
TXD5	PB18	UART5 RXD signal
RXD5	PB17	UART5 TXD signal
TXD6	PB14	UART6 RXD signal
RXD6	PB13	UART6 TXD signal
SWCLK	PB07	JLINK clock signal
SWDIO	PB11	JLINK data signal

Note

Note

The RXD signal of UARTx cannot be left floating, set to internal pull-up mode during software initialization

Figure 2.11 SWD debug interface circuit diagram

ButtonInterface

Power on/off and long press reset button

SF32LB58x series chipSwitch机SignalIt is recommended to use PB54，这样The short press power on/off function and long press reset function can be combined into one button。如Figure2-12所示，The design adopts a high-level active mode, the long press reset function requires pressing and holding for more than 10 seconds for the chip to automatically reset。

Figure2.12 Power on/off button circuit diagram

Function buttons or knobs

The SF32LB58x series chip supports function key input and knob signal input, and the key or knob signal needs to be pulled up。Button用法如Figure2.13所示。It can also support optical tracking sensors, and it is recommended to use the I2C4 interface，SignalConnection如Table2.19所示。

Table2.19 光追踪传感器Signal

I2CSignal	I/O	Detailed Description
INT	PA58	光追踪传感器InterruptSignalInput
SDA	PA59	光追踪传感器I2C DataSignal
SCL	PA60	光追踪传感器I2C Clock signal

Figure2.13 Function buttons or knobsCircuit Diagram

振动马达Interface

The SF32LB58x series chip supports multi-channel PWM output, which can be used as the drive signal for the vibration motor，Figure2.14所示为RecommendCircuit。

Figure2.14 振动马达Circuit Diagram

PBRInterface说明

The SF32LB58x series chip provides 6 PBR interfaces，其主要特点：

1. PBR0 will change from 0 to 1 during the boot stage, and is used to control some external LSWs. PBR1-PBR5 all default output 0；

2. PBR0-PBR5 can be used as outputs whether in standby or hibernate mode；

3. PBR0-PBR5 can output LPTIM signals；

4. PBR0-PBR5 can output 32K clock signals；

5. PBR0-PBR3 can be configured as inputs for wake-up signal input. When the MCU wakes up, no interrupts are received。

可唤醒Interrupt源

In light/deep sleep mode, all GPIOs of the SF32LB58x series chip support wake-up function，In standby and Hibernate mode, 16 wake-up interrupt sources are supported，如Table2.20所示，PA有6个Interrupt源，PB有10个Interrupt源。

Table2.20 Interrupt源ConnectionMethod

Interrupt源	I/O	Detailed Description
WKUP_PIN0	PB54	InterruptSignal0
WKUP_PIN1	PB55	InterruptSignal1
WKUP_PIN2	PB56	InterruptSignal2
WKUP_PIN3	PB57	InterruptSignal3
WKUP_PIN4	PB58	InterruptSignal4
WKUP_PIN5	PB59	InterruptSignal5
WKUP_PIN6	PA64	InterruptSignal6
WKUP_PIN7	PA65	InterruptSignal7
WKUP_PIN8	PA66	InterruptSignal8
WKUP_PIN9	PA67	InterruptSignal9
WKUP_PIN10	PA68	InterruptSignal10
WKUP_PIN11	PA69	InterruptSignal11
WKUP_PIN12	PBR0	InterruptSignal12
WKUP_PIN13	PBR1	InterruptSignal13
WKUP_PIN14	PBR2	InterruptSignal14
WKUP_PIN15	PBR3	InterruptSignal15

AudioInterface

The SF32LB58x series chip has various audio-related interfaces，如Table2.21所示，AudioInterfaceSignal有以下特点：

1. Supports 3 sets of I2S, where I2S1 can only be used as input, and I2S2 and I2S3 support both input and output；The three sets of I2S only support Master mode and do not support Slave mode；

2. I2S1 is recommended to connect to I2S MIC input；

3. I2S2 is recommended to connect to audio DAC；

4. I2S3 is recommended to connect to audio Codec；

5. Supports two channels of PDM MIC input；

6. Supports two channels of analog MIC input, with a DC blocking capacitor of at least 2.2uF required in between. The power supply for the analog MIC uses the MIC_BIAS of SF32LB58x；

7. Supports externally connected analog audio PA, the routing of the two DAC outputs should follow differential line routing, ensuring proper ground shielding treatment，还NeedNote：Trace Capacitor < 10pF, Length < 2cm。

8. Supports stereo analog headphone connection。

Table2.21 AudioSignalConnectionMethod

AudioSignal	I/O	Detailed Description
I2S1_LRCK	PA14	I2S1帧Clock
I2S1_SDI	PA18	I2S1DataInput
I2S1_BCK	PA23	I2S1位Clock
I2S2_LRCK	PA84	I2S2帧Clock
I2S2_SDI	PA86	I2S2DataInput
I2S2_SDO	PA82	I2S2DataOutput
I2S2_BCK	PA91	I2S2位Clock
I2S3_LRCK	PB31	I2S3帧Clock
I2S3_SDI	PB27	I2S3DataInput
I2S3_SDO	PB24	I2S3DataOutput
I2S3_BCK	PB30	I2S3位Clock
I2S3_MCLK	PB34	I2S3主Clock
PDM1_CLK	PA23	PDM1Clock
PDM1_DATA	PA18	PDM1Data
PDM2_CLK	PA25	PDM2Clock
PDM2_DATA	PA22	PDM2Data
AU_ADC1P	ADC1P	AnalogInput1P
AU_ADC1N	ADC1N	AnalogInput1N
AU_ADC2P	ADC2P	AnalogInput2P
AU_ADC2N	ADC2N	AnalogInput2N
AU_DAC1P	DAC1P	AnalogOutput1P
AU_DAC1N	DAC1N	AnalogOutput1N
AU_DAC2P	DAC2P	AnalogOutput2P
AU_DAC2N	DAC2N	AnalogOutput2N

The SF32LB58x analog MIC supports single-ended and differential input, with a 2.2uF capacitor in series in the middle。差分Input如Figure2.15所示，单端转差分Input如Figure2.16所示，其中AU_ADC1P, AU_ADC1N, AU_ADC2P, AU_ADC2N are connected to SF32LB58x，AU_ADC1P_IN和AU_ADC2P_IN是AnalogMIC或耳机AudioInput的Signal。

Figure2.15 差分AnalogAudioInputCircuit Diagram

Figure2.16 单端AnalogAudioInputCircuit Diagram

SF32LB58xAnalogAudioOutputCircuit Diagram如Figure2.17所示，其中AU_DAC1P, AU_DAC1N, AU_DAC2P, AU_DAC2N are the output signals of SF32LB58x，HP_DAC1P_OUT, HP_DAC1N_OUT, HP_DAC2P_OUT, HP_DAC2N_OUT are connected to the input pins of the stereo headphone PA，SPK_DAC1P_OUT and SPK_DAC1N_OUT are connected to the input pins of the analog audio PA。

Figure2.17 AnalogAudioOutputCircuit Diagram

AnalogMICInputConnection的Circuit Diagram如Figure2.18所示。

Figure2.18 AnalogMICCircuit Diagram

Stereo headphone connection circuit diagram is shown in Figure 2.19。

Figure2.19 立体声耳机Circuit Diagram

The connection circuit diagram of the analog audio PA is shown in Figure 2.20, using I2C3 to configure the registers of the analog audio PA。

Figure2.20 AnalogAudioPACircuit Diagram

The connection circuit diagram of the I2S audio PA is shown in Figure 2.21, using I2C3 to configure the registers of the I2S audio PA。

Figure2.21 I2SAudioPACircuit Diagram

USBInterface

The SF32LB58x series chip USB supports USB2.0 HS, and supports HOST and Device modes，It is required to connect TVS in parallel on USB DP and DM, and the junction capacitance of TVS should be less than 5pF，另外就是The DP, DM PCB traces are impedance controlled according to differential 90 ohms。The schematic diagram of USB interface connection is shown in Figure 2.22。

Figure2.22 USBInterfaceCircuit Diagram

PCBDesign指导

PCB PackageDesign

PackageSize

The SF32LB58x series chip package is BGA256, 8.5mmx6.5mmx0.94mm, with a pitch of 0.4mm，DetailedSize如Figure3.1所示。

Figure3.1 BGA256PackageSizeFigure

PackageShape

The package shape is shown in Figure 3.2。

Figure3.2 PackageShapeFigure

焊盘Design

PCB pad design information is shown in Figure 3.3。

Figure3.3 PCB焊盘焊盘DesignReference

PackageBALLMAP

The package BALLMAP information is shown in Figure 3.4。

Figure3.4 PackageBALLMAPInformation

Package基板

The package substrate BALL information is shown in Figure 3.5。 ​

Figure3.5 Package基板BALLInformation

PCBStack-upDesign

The layout of the SF32LB58x series chip supports single and double sides, and the PCB only supports HDI boards, not PTH boards：Recommend采用6HDI-2,The recommended reference stack structure is shown in Figure 3.6。

Figure3.6 ReferenceStack-upStructureFigure

PCBGeneralDesignRule

The general design rules for PCB are shown in Figure 3.7，Unit为mm。

Figure3.7 GeneralDesignRule

Blind holeDesign

The PCB blind hole design is shown in Figures 3.8 and 3.9，Unit为mm。

Figure3.8 1-2Blind holeDesign

Figure3.9 1-3Blind holeDesign

Buried holeDesign

The PCB buried hole design is shown in Figure 3.10，Unit为mm。

Figure3.10 Buried holeDesign

SF32LB58xChipTraceFan-out

The first two rows of balls in the BGA array are fanned out through the surface layer, and the other balls are fanned out through the inner layer via holes 如Figure3.11，3.12所示。

Figure3.11 Surface layerFan-outReferenceFigure

Figure3.12 Inner layerFan-outReferenceFigure

ClockInterfaceTrace

The crystal needs to be placed inside the shield, with a distance from the PCB board frame greater than 1mm,Try to keep away from devices with high heat generation, such as PA, Charge, PMU and other circuit devices, with a distance preferably more than 5MM，AvoidImpactCrystalFrequency offset，The forbidden wiring area spacing of the crystal circuit is greater than 0.25mm to avoid other metals and devices，如Figure3.13所示。

Figure3.13 CrystalLayoutFigure

It is recommended that the 48MHz crystal trace be on the surface layer with a length requirement controlled within the 3-10mm range,The line width is 0.075mm, it must be processed with a three-dimensional ground wrap, and its trace needs to be kept away from VBAT, DC/DC and high-speed signal lines。The area below the 48MHz crystal region and the adjacent layers should be treated as no-go zones, prohibiting other traces from passing through its area，如Figure3.14，3.15，3.16所示。

Figure3.14 48MHzCrystalSchematic diagram

Figure3.15 48MHzCrystalTraceModel

Figure3.16 48MHzCrystalTraceReference

It is recommended that the 32.768KHz crystal be placed on the surface layer, with a trace length controlled to ≤10mm, a line width of 0.075mm, and a parallel trace spacing between 32K_XI/32_XO ≥0.15mm. It must undergo three-dimensional ground wrapping treatment, and the area below and adjacent to the crystal must be kept clear, prohibiting other traces from passing through its region， 如Figure3.17，3.18，3.19所示。

Figure3.17 32.768KHzCrystalSchematic diagram

Figure3.18 32.768KHzCrystalTraceModel

Figure3.19 32.768KHzCrystalTraceReference

RFInterfaceTrace

The RF matching circuit should be placed as close to the chip end as possible, not near the antenna end. The filtering capacitor of the AVDD_BRF RF power supply should be placed as close to the chip pin as possible, and the capacitor grounding PIN should be directly connected to the main ground via a hole，RFSignal的π型网络的Schematic diagram和PCB分别如Figure3.20，3.21所示。

Figure3.20 π型网络以及Power supplyCircuitSchematic diagram

Figure3.21 π型网络以及Power supplyPCBLayout

It is recommended that the RF line be routed on the surface layer to avoid affecting RF performance by drilling through layers. The line width should preferably be greater than 10 mils, requiring three-dimensional ground wrapping treatment, avoiding acute angles and right angles. More shielding ground holes should be added on both sides of the RF line, and the RF line needs to have a 50-ohm impedance control，如Figure3.22,3.23所示。

Figure3.22 RFSignalCircuitSchematic diagram

Figure3.23 RFSignalPCBTrace

RF circuit routing prohibits DC-DC, VBAT, and high-speed digital signals from passing through its area, such as crystals, high-frequency clocks, and digital interface signals（I2C,SPI,SDIO,I2S，UART等）。 AVSS_RRF, AVSS_TRF, AVSS_TRF2, AVSS_VCO, AVSS_BB are the grounding pins for the RF circuit. It is necessary to ensure their good grounding. It is recommended to directly blind holes on their pads and connect them to the main ground，如Figure3.24a，3.24b所示。

Figure3.24a RFCircuitGroundingSignalSchematic diagram

Figure3.24b RFCircuitGroundingSignalPCBFigure

AudioInterfaceTrace

AVDD33_AUD is the pin that powers the audio interface, its filter capacitor should be placed close to its corresponding pin, and the filter capacitor’s ground pin should be well connected to the main ground. MIC_BIAS is the power supply circuit for the microphone of the audio interface, its corresponding filter capacitor should be placed close to the corresponding pin, and the filter capacitor’s ground pin should be well connected to the main ground. The AUD_VREF filter capacitor should be placed close to the pin，如Figure3.25a，3.25b所示。

Figure3.25a AudioCircuitPower supplySchematic diagram

Figure3.25b AudioCircuitPower supply滤波CircuitPCBDesign

AU_ADC1P/AU_ADC1N, AU_ADC2P/AU_ADC2N are two analog signal inputs. Corresponding circuit components should be placed as close to the corresponding pins as possible. Each P/N line should be routed in differential form, with the trace length as short as possible. Differential pair routing should undergo three-dimensional ground wrapping treatment, and strong interference signals from other interfaces should stay away from its routing，如Figure3.26a，3.26b所示。

Figure3.26a AnalogAudioInputSchematic diagram

Figure3.26b AnalogAudioInputPCBDesign

AU_DAC1P/AU_DAC1N, AU_DAC2P/AU_DAC2N are two analog signal outputs. Corresponding circuit components should be placed as close to the corresponding pins as possible. Each P/N line should be routed in differential form, with the trace length as short as possible and less than 2mm, the parasitic capacitance of the trace should be less than 10pf, the differential trace width should be 0.075mm, and the differential pair routing should undergo three-dimensional ground wrapping treatment. Strong interference signals from other interfaces should stay away from its routing，如Figure3.27a，3.27b所示。

Figure3.27a AnalogAudioOutputSchematic diagram

Figure3.27b AnalogAudioOutputPCBDesign

USB InterfaceTrace

AVDD33_USB is the power supply pin for the USB interface, its filter capacitor should be placed close to the pin, and the USB2_REXT calibration resistor should also be placed close to the pin. USB routing must first pass through the ESD device pin, then to the chip end, ensuring that the ESD device’s grounding PIN is well connected to the main ground. USB DP/DN should be routed in differential form, controlled at 90 ohms differential impedance, and undergo three-dimensional wrapping treatment，如Figure3.28a，3.28b所示。Figure2.29a为USBSignal的元件LayoutReferenceFigure，Figure3.29b为PCBTraceModel。

Figure3.28a USBSignalSchematic diagram

Figure3.28b USB signal PCB design

Figure3.29a USB signal device layout reference

Figure3.29b USB signal routing model

SDIO InterfaceTrace

SF32LB58X provides two SDIO interfaces, SDIO1 and SDIO2. All SDIO signal routings are kept together to avoid separation. The total routing length should be ≤50mm, and the length within a group should be controlled to ≤6mm. The clock signal of the SDIO interface needs to be processed with a three-dimensional ground wrap, and the DATA and CM signals also need to be wrapped with ground，如Figure3.30a，3.30b所示。

Figure3.30a SDIO1 interface circuit diagram

Figure3.30b SDIO1 PCB routing model

DSI InterfaceTrace

AVDD18_DSI is the power supply pin for the DSI interface, its filter capacitor is placed close to the pin, and the DSI_REXT calibration resistor is placed near the pin, The DSI interface routing follows the differential line form, requiring a differential impedance control of 100 ohms, and the clock and data need to be equalized in length. The intra-pair control for differential pairs should be ≤0.5mm, and inter-pair control should be ≤2mm; Each pair of differential lines needs to be processed with a three-dimensional ground wrap，如Figure3.31a，3.31b所示。

Figure3.31a DSI signal circuit diagram

Figure3.31b DSI signal PCB routing

DC-DC CircuitTrace

The power inductor and filter capacitor of the DC-DC circuit must be placed close to the chip’s pins. The BUCK_LX routing should be as short and thick as possible to ensure a small loop inductance for the entire DC-DC circuit. Multiple vias should be used to connect all DC-DC output filter capacitors’ ground pins to the main ground plane；The feedback line of the BUCK_FB pin cannot be too thin, it must be greater than 0.25mm. Copper laying is prohibited on the surface layer of the power inductor area, and the adjacent layer must be a complete reference ground to avoid other traces passing through the inductor area，如Figure3.32a，3.32b所示。

Figure3.32a DC-DC key component circuit diagram

Figure3.32b DC-DC key component PCB layout diagram

Power supply供电Trace

PVDD1 and PVDD2 are the power input pins of the chip’s built-in PMU module. The corresponding capacitors must be placed close to the pins, and the routing should be as thick as possible, not less than 0.5mm; PVSS1 and PVSS2 are the grounding pins of the PMU module. They must be connected to the main ground through vias to avoid floating and affecting the performance of the entire PMU，如Figure3.33a，3.33b所示。

Figure3.33a DC-DC circuit diagram

Figure3.33b DC-DC PCB routing

LDO和IOPower InputTrace

All LDO outputs and IO power input pin filter capacitors are placed close to the corresponding pins. Their trace width must meet the input current requirements, and the traces should be as short and thick as possible to reduce power ripple and improve system stability；如Figure3.14所示。

Figure3.34 Schematic diagram of LDO and IO input power routing

OtherInterfaceTrace

When the pin is configured as a GPADC pin signal, it must be processed with a three-dimensional ground wrap and kept away from other interfering signals, such as battery level circuits and temperature check circuits。如Figure3.35所示。

Figure3.35 GPADC circuit diagram

When the pin is configured as a clock input/output pin signal network, it must be processed with a three-dimensional ground wrap and kept away from other interfering signals, such as 32K output；如Figure3.36所示。

Figure3.36 32K clock output circuit diagram

SF32LB58X Chip地Trace

The ground network in the central area of the SF32LB58X chip needs to be fully connected with traces to ensure sufficient ground plane and connected to the main ground plane through blind/buried vias。如Figure3.37a，3.37b，3.37c，3.37d；

Figure3.37a Ground signal of the TOP layer under the chip

Figure3.37b Ground signal of the second layer under the chip

Figure3.37c Ground signal of the third layer under the chip

Figure3.37d Ground signal of the fourth layer under the chip

EMI&ESD routing

Avoid long-distance wiring on the outer surface of the shield，Especially for clock and power interference signals, try to route them in the inner layer，Surface routing is prohibited；ESD protection devices must be placed close to the corresponding pins of the connector，The signal trace should first pass through the ESD protection device pin，Avoid signal bifurcation，Did not pass the ESD protection pin，The ground pin of the ESD device must ensure via connection to the main ground，Ensure that the ground pad traces are short and thick，Reduce impedance to improve the performance of ESD devices。

Other

The USB charging cable test point must be placed in front of the TVS tube，The battery seat TVS tube is placed in front of the platform Its wiring must ensure that it passes through the TVS first and then to the chip end，如Figure3.38所示。

Figure3.38 Power supplyTVSLayoutReference

The ground pin of the TVS tube should avoid running a long line before connecting to the ground，如Figure3.39所示。

Figure3.39 TVSTraceReference

In order to ensure that the solder mask does not go onto the pad, affecting the reliability of soldering，The vias on the BGA pads are required to be drilled in the central area of the BGA balls。Avoid misalignment，如Figure3.40所示。

Figure3.40 BGA打孔Schematic

In order to improve the yield of processability，Optimize the PCB design by referring to Figures 3.41a and 3.41b。

Figure3.41a BGA BALL连线ReferenceFigure一

Figure3.41b BGA BALL连线ReferenceFigure二

Revision history

Version	Date	Release notes
0.0.1	1/2025	Draft version