SF32LB52X-Hardware Design Guide

Attention

This document is compatible with chips with the suffix letters B, E, G, J, H, and uses a 3.3V power supply。

For chips with the suffix numbers 0, 3, 5, 7, they belong to the SF32LB52x series, use lithium battery power supply, and support USB charging。应该参照Hardware Design Guide

基本介绍

The main purpose of this article is to help developers complete the development of watch solutions based on the SF32LB52X series of chips。This article focuses on the precautions related to hardware design during the solution development process, aiming to minimize the workload of developers and shorten the product’s time to market。

SF32LB52X is a series of highly integrated, high-performance MCU chips for ultra-low power artificial intelligence Internet of Things (AIoT) scenarios。The chip adopts a big.LITTLE architecture based on the Arm Cortex-M33 STAR-MC1 processor, integrating a high-performance 2D/2.5D graphics engine, artificial intelligence neural network accelerator, dual-mode Bluetooth 5.3, and audio CODEC，可广泛用于腕带类可穿戴电子设备、智能移动终端、智能家居等各种应用场景。

Attention

SF32LB52X is the regular power supply version of the SF32LB52 series, with a power supply voltage of 2.97~3.63V, and does not support charging，具体包含如下型号：
SF32LB52BU36，合封1MB QSPI-NOR Flash
SF32LB52EUB6，合封4MB OPI-PSRAM
SF32LB52GUC6，合封8MB OPI-PSRAM
SF32LB52JUD6，合封16MB OPI-PSRAM

The peripheral resources of the processor are as follows：

• 45x GPIO

• 3x UART

• 4x I2C

• 2x GPTIM

• 2x SPI

• 1x I2SAudio interface

• 1x SDIO 存储接口

• 1x PDMAudio interface

• 1x 差分模拟音频输出

• 1x 单端模拟音频输入

• 支持单/双/四数据线SPI显示接口，支持串行JDI模式显示接口

• 支持带GRAM和不带GRAM的两种显示屏

• 支持UART下载和软件调试

封装

表2-1 Package Information Table

封装名称	尺寸	管脚间距
QFN68L	7x7x0.85 mm	0.35 mm

图2-1 QFN68L管脚分布

Typical Application Scheme

The figure below is a block diagram of a typical SF32LB52X sports watch, with main functions including display, storage, sensors, vibration motor, and audio input and output。

图3-1 运动手表组成框图

Note

• The big.LITTLE dual-CPU architecture takes into account both high performance and low power consumption design requirements

• The chip integrates charging management and PMU modules

• Supports QSPI interface TFT or AMOLED display, with a maximum resolution of 512*512

• Supports PWM backlight control

• Supports external QSPI NOR/NAND Flash and SD NAND Flash memory chips

• Supports dual-mode Bluetooth 5.3

• Supports analog audio input

• Supports analog audio output

• Supports PWM vibration motor control

• Supports SPI/I2C interface acceleration/geomagnetic/gyroscope sensors

• Supports SPI/I2C interface heart rate/oxygen saturation/electrocardiogram/geomagnetic sensors

• Supports UART debugging print interface and burning tools

• Supports Bluetooth HCI debugging interface

• Supports one-to-many program burning in the production line

• Supports crystal calibration function in the production line

• Supports OTA online upgrade function

原理图设计指导

Power Supply

Processor Power Requirements

表4-1 Power Supply Requirements

Power Supply管脚	最小电压(V)	典型电压(V)	最大电压(V)	最大电流(mA)	详细描述
PVDD	2.97	3.3	3.63	150	PVDD系统Power Supply输入，接10uF电容
BUCK_LX	-	1.25	-	50	BUCK输出脚，接4.7uH电感
BUCK_FB	-	1.25	-	50	BUCK反馈和内部Power Supply输入脚，接电感另一端，且外接4.7uF电容
VDD_VOUT1	-	1.1	-	50	内部LDO，外接4.7uF电容，内部Power Supply，不给外设供电
VDD_VOUT2	-	0.9	-	20	内部LDO，外接4.7uF电容，内部Power Supply，不给外设供电
VDD_RET	-	0.9	-	1	内部LDO，外接0.47uF电容，内部Power Supply，不给外设供电
VDD_RTC	-	1.1	-	1	内部LDO，外接1uF电容，内部Power Supply，不给外设供电
VDDIOA	1.71	1.8/3.3	3.63	-	GPIOPower Supply输入，外接1uF电容
AVDD33	2.97	3.3	3.63	100	3.3V模拟Power Supply输入，外接4.7uF电容
AVDD33_AUD	2.97	3.3	3.63	50	3.3V音频Power Supply输入，外接2.2uF电容
VDD_SIP	1.71	1.8/3.3	3.63	30	内部LDO，或者外部Power Supply输入(1) ，外接1uF电容
AVDD_BRF	2.97	3.3	3.63	100	模拟Power Supply输入，外接4.7uF电容
MIC_BIAS	1.4	-	2.8	-	MICPower Supply输出，外接1uF电容

Note

⁽¹⁾

• SF32LB52BU36，需要外供1.8V或3.3V

• SF32LB52BU56，需要外供3.3V

• SF32LB52E/G/JUx6，PVDD=1.8V时，内部LDO无法使用，需要外供1.8V；PVDD=3.3V时，内部LDO直接供电，无需外供

Important

When the system uses Hibernate mode, the VDD_SIP power supply must be turned off, otherwise there will be a risk of leakage on the I/O of the stacked storage。VDD_SIP的Power Supply控制信号请使用专用的PA21引脚。

Processor BUCK Inductor Selection Requirements

Key Parameters of Power Inductor

Important

L(电感值) = 4.7uH ± 20%，DCR(直流阻抗) ≦ 0.4 ohm，Isat(饱和电流) ≧ 450mA。

How to reduce standby power consumption

In order to meet the long battery life requirements of watch products, it is recommended to use load switches for dynamic power management of various functional modules in the hardware design；如果是常开的模块或通路，选择合适的器件以降低静态电流。

During the design, attention should be paid to controlling the hardware default state of the GPIO pins of the power switch, and adding pull-up and pull-down resistors at the M level to ensure that the load switch is closed by default。

In terms of power device selection, LDO and Load Switch chips should choose devices with small static current Iq and shutdown current Istb. Especially for power chips that are always on, attention must be paid to the Iq parameter。

Processor Operating Modes and Wake-up Sources

表4-4 CPU Mode Table

工作模式	CPU	外设	SRAM	IO	LPTIM	唤醒源	唤醒时间
Active	Run	Run	可访问	可翻转	Run	-	-
Sleep	Stop	Run	可访问	可翻转	Run	任意中断	<0.5us
DeepSleep	Stop	Stop	不可访问，全保留	电平Hold	Run	RTC，唤醒IO，GPIO，LPTIM，蓝牙	250us
Standby	Reset	Reset	不可访问，全保留	电平Hold	Run	RTC，唤醒IO，LPTIM，蓝牙	1ms
Hibernate	Reset	Reset	不可访问，不保留	高阻	Reset	RTC，唤醒IO	>2ms

As shown in Table 4-5, the full series of chips support 15 interrupt sources that can wake up in Standby and Hibernate modes。

表4-5 Interrupt wake up source Table

中断源	管脚	详细描述
LWKUP_PIN0	PA24	Interrupt signal0
LWKUP_PIN1	PA25	Interrupt signal1
LWKUP_PIN2	PA26	Interrupt signal2
LWKUP_PIN3	PA27	Interrupt signal3
LWKUP_PIN10	PA34	Interrupt signal10
LWKUP_PIN11	PA35	Interrupt signal11
LWKUP_PIN12	PA36	Interrupt signal12
LWKUP_PIN13	PA37	Interrupt signal13
LWKUP_PIN14	PA38	Interrupt signal14
LWKUP_PIN15	PA39	Interrupt signal15
LWKUP_PIN16	PA40	Interrupt signal16
LWKUP_PIN17	PA41	Interrupt signal17
LWKUP_PIN18	PA42	Interrupt signal18
LWKUP_PIN19	PA43	Interrupt signal19
LWKUP_PIN20	PA44	Interrupt signal20

时钟

The chip requires two external clock sources, a 48MHz main crystal and a 32.768KHz RTC crystal. The specific specifications and selection of the crystals are as follows：

Important

表4-6 晶体规格要求

晶体	晶体规格要求	详细描述
48MHz	CL≦12pF（推荐值7pF）△F/F0≦±10ppmESR≦30 ohms（推荐值22ohms）	The power consumption of the crystal oscillator is related to CL and ESR. The smaller the CL and ESR, the lower the power consumption. For optimal power consumption performance, it is recommended to use the recommended valuesCL≦7pF，ESR≦22 ohms.晶体旁边预留并联匹配电容,当CL<9pF时，无需焊接电容
32.768KHz	CL≦12.5pF（推荐值7pF）△F/F0≦±20ppm ESR≦80k ohms（推荐值38Kohms）	The power consumption of the crystal oscillator is related to CL and ESR. The smaller the CL and ESR, the lower the power consumption. For optimal power consumption performance, it is recommended to use the recommended valuesCL≦9pF，ESR≦40K ohms.晶体旁边预留并联匹配电容,当CL<12.5pF时，无需焊接电容

表4-7 推荐晶体列表

型号	厂家	参数
E1SB48E001G00E	Hosonic	F0 = 48.000000MHz，△F/F0 = -6 ~ 8 ppm，CL = 8.8 pF，ESR = 22 ohms Max TOPR = -30 ~ 85℃，Package =（2016 公制）
ETST00327000LE	Hosonic	F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm，CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制）
SX20Y048000B31T-8.8	TKD	F0 = 48.000000MHz，△F/F0 = -10 ~ 10 ppm，CL = 8.8 pF，ESR = 40 ohms Max TOPR = -20 ~ 75℃，Package =（2016 公制）
SF32K32768D71T01	TKD	F0 = 32.768KHz，△F/F0 = -20 ~ 20 ppm，CL = 7 pF，ESR = 70K ohms Max TOPR = -40 ~ 85℃，Package =（3215 公制）

射频

The RF trace requirement is for a characteristic impedance of 50 ohms。如果天线是匹配好的，射频上无需再增加额外器件。It is recommended to reserve a π-type matching network during design for spurious filtering or antenna matching。

图4-7 射频电路图

显示

The chip supports 3-Line SPI, 4-Line SPI, Dual data SPI, Quad data SPI, and serial JDI interfaces。Supports 16.7M-colors (RGB888), 262K-colors (RGB666), 65K-colors (RGB565), and 8-color (RGB111) Color depth modes。Supports a maximum resolution of 512RGBx512。

表4-8 LCD driver支持列表

型号	厂家	分辨率	类型	接口
RM69090	Raydium	368*448	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，MIPI-DSI
RM69330	Raydium	454*454	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，8-bits 8080-Series MCU ，MIPI-DSI
ILI8688E	ILITEK	368*448	Amoled	Quad data SPI，MIPI-DSI
SH8601A	晟合技术	454*454	Amoled	3-Line SPI，4-Line SPI，Dual data SPI， Quad data SPI，8-bits 8080-Series MCU ，MIPI-DSI
SPD2012	Solomon	356*400	TFT	Quad data SPI
GC9C01	Galaxycore	360*360	TFT	Quad data SPI
GC9B71	Galaxycore	320*380	TFT	Quad data SPI
ST77903	Sitronix	400*400	TFT	Quad data SPI
ICNA3311	Chipone	454*454	Amoled	Quad data SPI
FT2308	FocalTech	410*494	Amoled	Quad data SPI

SPI/QSPI显示接口

芯片支持 3/4-wire SPI和Quad-SPI 接口来连接LCD显示屏，The description of each signal is shown in the table below。

表4-9 SPI/QSPI 信号连接方式

spi信号	管脚	详细描述
CSx	PA03	Enable signal
WRx_SCL	PA04	Clock signal
DCx	PA06	4-wire SPI 模式下的Data/command signalQuad-SPI 模式下的Data 1
SDI_RDx	PA05	3/4-wire SPI 模式下的Data input signalQuad-SPI 模式下的Data 0
SDO	PA05	3/4-wire SPI 模式下的Data output signal请和SDI_RDX短接到一起
D[0]	PA07	Quad-SPI 模式下的Data 2
D[1]	PA08	Quad-SPI 模式下的Data 3
RESET	PA00	Reset display screen signal
TE	PA02	Tearing effect to MCU frame signal

JDI显示接口

The chip supports a parallel JDI interface to connect to the LCD display，如下表所示。

表4-10 并行JDI屏信号连接方式

JDI信号	I/O	详细描述
JDI_VCK	PA39	Shift clock for the vertical driver
JDI_VST	PA08	Start signal for the vertical driver
JDI_XRST	PA40	Reset signal for the horizontal and vertical driver
JDI_HCK	PA41	Shift clock for the horizontal driver
JDI_HST	PA06	Start signal for the horizontal driver
JDI_ENB	PA07	Write enable signal for the pixel memory
JDI_R1	PA05	Red image data (odd pixels)
JDI_R2	PA42	Red image data (even pixels)
JDI_G1	PA04	Green image data (odd pixels)
JDI_G2	PA43	Green image data (even pixels)
JDI_B1	PA03	Blue image data (odd pixels)
JDI_B2	PA02	Blue image data (even pixels)

触摸和背光接口

芯片支持I2C格式的触摸屏控制接口和触摸状态中断输入，同时支持1路PWM信号来控制背光Power Supply的使能和亮度，如下表所示。

表4-11 触摸和背光控制连接方式

触摸屏和背光信号	管脚	详细描述
Interrupt	PA43	Touch status interrupt signal (can wake up)
I2C1_SCL	PA42	Touch screen I2C clock signal
I2C1_SDA	PA41	Touch screen I2C data signal
BL_PWM	PA01	Backlight PWM control signal
Reset	PA44	Touch reset signal

存储

存储器连接接口描述

The chip supports four types of external storage media: SPI NOR Flash, SPI NAND Flash, SD NAND Flash, and eMMC。

表4-12 SPI NOR/NAND Flash信号连接

Flash 信号	I/O信号	详细描述
CS#	PA12	Chip select, active low.
SO	PA13	Data Input (Data Input Output 1)
WP#	PA14	Write Protect Output (Data Input Output 2)
SI	PA15	Data Output (Data Input Output 0)
SCLK	PA16	Serial Clock Output
Hold#	PA17	Data Output (Data Input Output 3)

表4-13 SD NAND Flash和eMMC信号连接

Flash 信号	I/O信号	详细描述
SD2_CMD	PA15	Command signal
SD2_D1	PA17	Data 1
SD2_D0	PA16	Data 0
SD2_CLK	PA14	Clock signal
SD2_D2	PA12	Data 2
SD2_D3	PA13	Data 3

启动设置

The chip supports booting from internally integrated Spi NOR Flash, external Spi NOR Flash, external Spi NAND Flash, external SD NAND Flash, and external eMMC。其中：

• SF32LB52AUx6 has internally integrated flash and boots from the internal flash by default

• SF32LB52D/F/HUx6 has internally integrated PSRAM and must boot from external storage media

图4-8 Bootstrap管脚推荐电路图

表4-14 Boot option settings

Bootstrap[1] (PA13)	Bootstrap[0] (PA17)	Boot From ext memory
L	L	SPI NOR Flash
L	H	SPI NAND Flash
H	X	SD NAND Flash
H	H	eMMC

启动存储介质Power Supply控制

The chip supports power switch control for boot storage media to reduce power consumption during shutdown。Power Supply开关的使能管脚必须使用PA21来控制，开关的使能电平要求是[高打开，低关闭]。

Important

• SF32LB52AUx6 has internally integrated flash, please add a power switch to VDD_SIP。

• SF32LB52D/F/HUx6 has internally integrated PSRAM, if PVDD=3.3V and VDD_SIP is powered by the internal LDO, a power switch can be omitted for VDD_SIP if PVDD=1.8V, a power switch must be added for VDD_SIP。

• The power supply for externally provided storage media is independent of VDD_SIP, and a separate power switch should be added。

• The eMMC chip has two power domains, VCC and VCCQ，方式1：可以2个Power Supply一起做控制，关机功耗低，但eMMC在sleep时恢复慢，CPU平均功耗高；方式2：可以单独控制VCC，VCCQ常供不断电，关机功耗比方式1高，但eMMC在sleep时恢复快，CPU平均功耗比方式1低。

• The enable pin for the power switch of all memory related to startup must be controlled by PA21。

• In the reference design, pull-up resistor positions for PA13 and PA17 are reserved. Choose pull-up resistors based on the type of storage medium, with a recommended resistance of 7.5K。

Button

Power on/off button

The PA34 of the chip supports the long press reset function, which can be designed into a button to realize the power on/off + long press reset function。The long press reset function of PA34 requires a high level to be effective, so it is designed to be pulled down by default to low, and the level will be high after the button is pressed，如图 {number}所示。

图4-9 Power on/off button电路图

Mechanical knob button

图4-10 Power on/off button电路图

Vibration motor

The chip supports PWM output to control the vibration motor。

图4-11 Vibration motor电路图

Audio interface

芯片的音频相关接口，如表4-15所示，Audio interface信号有以下特点：

1. Supports a single-ended ADC input, externally connected to an analog MIC, a DC-blocking capacitor with a capacitance value of at least 2.2uF needs to be added in the middle, and the power supply of the analog MIC is connected to the MIC_BIAS power output pin of the chip；

2. Supports a differential DAC output, externally connected to an analog audio PA, the wiring of the DAC output should follow the differential line routing, and the ground shielding treatment should be done well，还需要注意：Trace Capacitor < 10pF, Length < 2cm。

表4-15 音频信号连接方式

音频信号	管脚	详细描述
BIAS	MIC_BIAS	麦克风Power Supply
AU_ADC1P	ADCP	单端Analog MIC输入
AU_DAC1P	DACP	差分模拟输出P
AU_DAC1N	DACN	差分模拟输出N

The recommended circuit for analog MEMS MIC is shown in Figure 4-12, and the recommended circuit for analog ECM MIC single-ended is shown in Figure 4-13, where MEMS_MIC_ADC_IN and ECM_MIC_ADC_IN are connected to the ADCP input pin of SF32LB52x。

图4-12 模拟MEMS MIC单端输入电路图

图4-13 模拟ECM单端输入电路图

The recommended circuit for analog audio output is shown in Figure 4-14, note that the differential low-pass filter within the dotted line should be placed close to the chip end。

图4-14 模拟音频PA电路图

传感器

The chip supports sensors such as heart rate, acceleration, and geomagnetism。The power supply of the sensor selects a Load Switch with a relatively small Iq to control the power switch。

UART和I2C管脚设置

The chip supports arbitrary pin UART and I2C function mapping, all PA interfaces can be mapped to UART or I2C function pins。

GPTIM管脚设置

The chip supports arbitrary pin GPTIM function mapping, all PA interfaces can be mapped to GPTIM function pins。

调试和下载接口

The chip supports the DBG_UART interface for downloading and debugging, and connects to the PC through the UART to USB Dongle board of the 3.3V interface。

表4-16 调试口连接方式

DBG信号	管脚	详细描述
DBG_UART_RXD	PA18	Debug UART 接收
DBG_UART_TXD	PA19	Debug UART 发送

产线烧录和晶体校准

Sich Technology provides an offline downloader to complete the burning of the production line program and crystal calibration. When designing the hardware, please note that at least the test points should be reserved：PVDD、GND、AVDD33、DB_UART_RXD、DB_UART_RXD，PA01。

For detailed burning and crystal calibration, see the “**_Offline Downloader User Guide.pdf” document, which is included in the development materials package。

Schematic and PCB drawing checklist

See “Schematic checklist.xlsx” and “PCB checklist.xlsx” documents, included in the development materials package。

PCB设计指导

PCB封装设计

The QFN68L package size of the SF32LB52X series chip: 7mmX7mmx0.85mm number of pins: 68 PIN pitch: 0.35mm。 详细尺寸如图5-1所示。

图5-1 QFN68L封装尺寸图

图5-2 QFN68L封装形状图

图5-3 QFN68L封装PCB焊盘设计参考图

PCB叠层设计

The SF32LB52X series chip supports single/double-sided layout, devices can be placed on a single side, and capacitors can also be placed on the back of the chip。PCB supports PTH via design, it is recommended to use 4-layer PTH, the recommended reference stack structure is shown in Figure 5-4。

图5-4 参考叠层结构图

PCB通用设计规则

The general design rules for PTH board PCB are shown in Figure 5-5。

图5-5 通用设计规则

PCB走线扇出

QFN package signal fan-out, all pins are completely fanned out through the surface layer, as shown in Figure 5-6。

如图5-6 表层扇出参考图

时钟接口走线

The crystal needs to be placed inside the shield, the distance from the PCB frame is greater than 1mm, try to stay away from devices with large heat generation, such as PA, Charge, PMU and other circuit devices, the distance should be more than 5mm to avoid affecting the crystal frequency deviation, the crystal circuit forbidden area spacing is greater than 0.25mm to avoid other metals and devices, as shown in Figure 5-7。

图5-7 晶体布局图

It is recommended that the 48MHz crystal trace go through the surface layer, the length requirement is controlled in the 3-10mm range, the line width is 0.1mm, it must be processed with a three-dimensional ground wrap, and stay away from VBAT, DC/DC and high-speed signal lines。The area below the 48MHz crystal area and the adjacent layers are prohibited from being empty, and other traces are prohibited from passing through its area, as shown in Figures 5-8, 5-9, and 5-10。

Figure 5-8 48MHz crystal schematic diagram

Figure 5-9 48MHz crystal wiring model

Figure 5-10 48MHz crystal wiring reference

It is recommended that the 32.768KHz crystal wiring be on the surface layer, with a length controlled to ≤10mm and a line width of 0.1mm.The parallel wiring distance for 32K_XI/32_XO should be ≥0.15mm, and must be processed with a three - dimensional ground wrap.晶体区域下方表层及临层做禁空处理，禁止其它走线从其区域走，如图5-11，5-12，5-13所示。

图5-11 32.768KHz晶体原理图

图5-12 32.768KHz晶体走线模型

图5-13 32.768KHz晶体走线参考

射频接口走线

The RF matching circuit should be placed as close to the chip end as possible, not close to the antenna end.The filtering capacitor of the AVDD_BRF RF power supply should be placed as close to the chip pin as possible, and the grounding pin of the capacitor should be directly connected to the main ground through a via.RF信号的π型网络的原理图和PCB分别如图5-14，5-15所示。

图5-14 π型网络以及Power Supply电路原理图

图5-15 π型网络以及Power SupplyPCB布局

It is recommended that the RF wiring be on the surface layer to avoid affecting RF performance by drilling through layers. The line width should be greater than 10mil, and three - dimensional ground wrapping is required to avoid acute angles and right angles.射频线做50欧阻抗控制，两边多打屏蔽地孔，如图5-16, 5-17所示。

图5-16 RF信号电路原理图

图5-17 RF信号PCB走线图

Audio interface走线

AVDD33_AUD is the power supply pin for audio, and its filter capacitor is placed close to the corresponding pin so that the grounding pin of the filter capacitor can be well connected to the main ground of the PCB.MIC_BIAS is the power output pin for powering the microphone peripheral, and its corresponding filter capacitor is placed close to the corresponding pin.同样AUD_VREF管脚的滤波电容也靠近管脚放置，如图5-18a，5-18b所示。

图5-18a 音频相关Power Supply滤波电路

图5-18b 音频相关Power Supply滤波电路PCB参考走线

模拟信号输入ADCP管脚，对应电路器件尽量靠近芯片管脚放置，走线线长尽量短，做立体包地处理，远离其它强干扰信号，如图5-19a，5-19b所示。

图5-19a 模拟音频输入原理图

图5-19b 模拟音频输入PCB设计

模拟信号输出DACP/DACN管脚，对应电路器件尽量靠近芯片管脚放置，每一路P/N需要按照差分线形式走线，走线线长尽量短，寄生电容小于10pf，需做立体包地处理，远离其它强干扰信号，如图5-20a，5-20b所示。

图5-20a 模拟音频输出原理图

图5-20b 模拟音频输出PCB设计

USB接口走线

The USB wiring PA35 (USB DP)/PA36 (USB_DN) must first pass through the ESD device pin and then to the chip end, ensuring that the grounding pin of the ESD device can be well connected to the main ground.走线需按照差分线形式走，并做90欧差分阻抗控制，且做立体包处理，如图5-21a，5-21b所示。

5-21a USB信号原理图

5-21b USB信号PCB设计

图5-22a为USB信号的元件布局参考图，图5-22b为PCB走线模型。

图5-22a USB信号器件布局参考

图5-22b USB信号走线模型

SDIO接口走线

SDIO信号走线尽量一起走，避免分开走，整个走线长度≤50mm, 组内长度控制≤6mm。SDIO接口Clock signal需立体包地处理，DATA和CMD信号也需要包地处理，如图5-23a，5-23b所示。

Figure 5-23a SDIO Interface Circuit Diagram

Figure 5-23b SDIO PCB Trace Model

DCDC电路走线

The power inductor and filter capacitor of the DC-DC circuit must be placed close to the chip’s pins。The BUCK_LX trace should be as short and thick as possible to ensure a small loop inductance for the entire DC-DC circuit；The feedback line of the BUCK_FB pin cannot be too thin, it must be greater than 0.25mm。All grounding pins of the DC-DC output filter capacitors should have multiple vias connecting to the main ground plane。Copper is prohibited on the surface layer of the power inductor area, and the adjacent layer must be a complete reference ground to avoid other traces passing through the inductor area，如图5-24a，5-24b所示。

Figure 5-24a DC-DC Key Component Circuit Diagram

Figure 5-24b DC-DC Key Component PCB Layout Diagram

Power Supply供电走线

PVDD is the power input pin of the chip’s built-in PMU module the corresponding capacitor must be placed close to the pin, and the trace should be as thick as possible, not less than 0.4mm，如图5-25所示。

Figure 5-25 PVDD Power Trace Diagram

The filter capacitors for pins such as AVDD33, VDDIOA, VDD_SIP, AVDD33_AUD, and AVDD_BRF should be placed close to their respective pins the trace width must meet the input current requirements, and the traces should be as short and thick as possible to reduce power ripple and improve system stability。

其它接口走线

For pins configured as GPADC pin signals, three-dimensional ground wrapping treatment is required, keeping away from other interfering signals such as battery level circuits and temperature check circuits。

EMI&ESD

• Avoid long-distance traces on the outer surface of the shield, especially for interference signals like clock and power which should preferably be routed on inner layers, and are prohibited on the surface layer。

• ESD protection devices must be placed close to the corresponding connector pins signal traces should pass through the ESD protection device pins first to avoid signal branching without passing through the ESD protection pins。

• The grounding pin of the ESD device must ensure via connection to the main ground, ensuring that the ground pad traces are short and thick to reduce impedance and enhance the performance of the ESD device。

其它

The USB charging cable test point must be placed in front of the TVS tube, and the battery seat TVS tube should be placed in front of the platform with its wiring ensuring to pass through the TVS first and then to the chip end，如图5-27所示。

Figure 5-27 Power TVS Layout Reference

Figure 5-28 TVS Trace Reference

The grounding pin of the TVS tube should avoid long traces before connecting to the ground，如图5-28所示。

修订历史

版本	日期	发布说明
0.0.1	10/2024	初始版本