15 I2S;related;

15.1 MCLK;output;frequency;翻倍

1，The 49.152M frequency division ratio SPCLK_DIV of the PLL changes from 8 to 4, and the MCLK increases from 6.144M to 12.288M;

#ifdef DOUBLE_MCLK;    
    __HAL_I2S;_SET_SPCLK_DIV(hi2s, 4);   // set to 12.288M to i2s (49.152M/4=12.288M)  PLL; 
#else
    __HAL_I2S;_SET_SPCLK_DIV(hi2s, 8);   // set to 6.144M to i2s   PLL;
#endif

2，The corresponding bclk duty and lrck duty are both doubled, so as to ensure that after the MCLK is doubled, other clock frequencies remain unchanged; as follows;，corresponding;structure;中CLK_DIV_T的as follows;value;都increase;一倍

uint16_t  lr_clk_duty_high;   /*!<  LRCK duty cycle high;   */
uint16_t  lr_clk_duty_low;    /*!<  RX LRCK duty cycle low;   */
uint16_t  blck_duty;          /*!<  bit clock duty cycle;   */

The original {48000, 64, 64, 2} is changed to {48000, 128, 128, 4}, and other sampling rate configurations are also modified in the same way;

#ifdef DOUBLE_MCLK;
static CLK_DIV_T  txrx_clk_div[9]  = {{48000, 128, 128,  4}, {44100, 128, 128,  4}, {32000, 192, 192,  6}, {24000, 256, 256, 8}, {22050, 256, 256,  8},
    {16000, 384, 384, 12}, {12000, 512, 512, 16}, {11025, 512, 512, 16}, { 8000, 768, 768, 24}
};
#else
static CLK_DIV_T  txrx_clk_div[9]  = {{48000, 64, 64,  2}, {44100, 64, 64,  2}, {32000, 96, 96,  3}, {24000, 128, 128, 4}, {22050, 128, 128,  4},
    {16000, 192, 192, 6}, {12000, 256, 256, 8}, {11025, 256, 256, 8}, { 8000, 384, 384, 12}
};