SPIScreen参数配置

接口说明

The software first divides into two categories based on whether the SPI interface has a physical D/CX line：LCDC_INTF_SPI_DCX_xxxAndLCDC_INTF_SPI_NODCX_xxx, 然After再根据批量送Data时（即0x2C/0x3C指令）,用到TheData线分成1~4DATA，最After再根据Whether or notDDR、Whether or notNeedPTC辅助，加上DDR, AUXThe字样。

One般来说3-wire SPI refers to those without a physical D/CX line, and 4-wire SPI has a physical D/CX line。

The pinmux of the D/CX line is generally LCDC_SPI_DIO1。

SPI接口The命令读写都Is单线Mode，只Is批量送数时（0x2c/0x3c指令）DataCanSupport1~4线并行。

接口名称

接口Whether or notHave物理TheD/CX线

0x2C/0X3C批量送数并行TheData线数

Other

LCDC_INTF_SPI_DCX_1DATA

Is

1

-

LCDC_INTF_SPI_DCX_2DATA

Is

2

-

LCDC_INTF_SPI_DCX_4DATA

Is

4

-

LCDC_INTF_SPI_DCX_4DATA_AUX

Is

4

ramlessScreen

LCDC_INTF_SPI_DCX_DDR_4DATA

Is

4

DDRMode

LCDC_INTF_SPI_NODCX_1DATA

否

1

-

LCDC_INTF_SPI_NODCX_2DATA

否

1

-

LCDC_INTF_SPI_NODCX_4DATA

否

1

-

Explanation of screen parameter configuration

4线/3线 SPI接口

static LCDC_InitTypeDef lcdc_int_cfg =
{
/*
    3-wire SPI mode, bulk data transfer with 2 data lines
*/
    .lcd_itf = LCDC_INTF_SPI_NODCX_2DATA,
/*  Selection of QSPI clk frequency, which is the frequency after dividing the hcpu main frequency，比如hcpu主频240Mhz，Be able to得到The频率只Can为40/48/60/80,如果设置62Mhz，实际Will设置为60Mhz */
    .freq = 24000000,
    .color_mode = LCDC_PIXEL_FORMAT_RGB565,

    .cfg = {
        .spi = {
            .dummy_Clock = 0, /* IsInQSPI读ModeUnder，配置cmdAnddata之间EmptyTheclk数量，默认为0，不用修改 */
/* This option is used to avoid image tearing，（出现撕裂原因：ScreenReadRAMData时，QSPI也In往RAM送数） */
#ifdef LCD_ST7789P3_VSYNC_ENABLE				
            .syn_mode = HAL_LCDC_SYNC_VER,/* Enable checking the TE signal sent by the screen and synchronize it with RAM data transfer，打开This配置，如果ScreenNoTE信号输出，Will出现No法给RAM送数，出现死机 */
#else
			.syn_mode = HAL_LCDC_SYNC_DISABLE,/* Disable checking the TE signal sent by the screen. Use this configuration when initially debugging the screen driver without considering tearing issues */
#endif
/*
This配置In选择HAL_LCDC_SYNC_VERAfter，才Have意义，用于配置TE（Vsync）信号来时The信号Duodecillion性，
Configured as 1, TE is normally at a low level, and data can be transferred to RAM when TE is at a high level 
*/
            .vsyn_polarity = 0,
            .vsyn_delay_us = 1000,/* This configuration is meaningful only after selecting HAL_LCDC_SYNC_VER and is used to configure how many microseconds the TE signal high level will delay before transferring data to RAM*/
            .hsyn_num = 0,/* This configuration is meaningful only after setting .syn_mode to HAL_LCDC_SYNC_VERHOR and is used to configure how many clk pulses after the TE signal high level before transferring data to RAM */
/*
1. When reading data via QSPI, CMD will be output from D0, but the read-back data will be output from D0-D3 for different screen driver ICs. This configuration is for compatibility with different screen driver ICs
2. Can配置为0-3，参考Screen驱ICThe规格书，选择QSPI对Shouldread时FromD0 - D3进行Read信号 
*/            
            .readback_from_Dx = 0,
        },
    },
};

Under图Is4线TENo使CanThe波形图,Can见到TEThe波形No跟SPITheCSUnder降沿进行对齐 alt text

Frame rate testing method

  • Enable the HAL_LCDC_SYNC_VER configuration, the SPI timing is shown in the figure below, and the screen delivery will align with TE

  • In UI interfaces with very high frame rates, check the frequency of the TE test, which represents the frame rate achieved for screen refreshing alt text

QSPI接口

#ifdef LCDC_USE_DDR_QSPI
    #define QAD_SPI_ITF LCDC_INTF_SPI_DCX_DDR_4DATA
    #define QAD_SPI_ITF_FREQ   40000000
#else
    #define QAD_SPI_ITF LCDC_INTF_SPI_DCX_4DATA
    #define QAD_SPI_ITF_FREQ   48000000
#endif
static LCDC_InitTypeDef lcdc_int_cfg_spi =
{
 /*
 1. DDR（qspiTheclk双沿送数方式）选择 LCDC_INTF_SPI_DCX_DDR_4DATA
2. SDR（qspiTheclk单沿送数方式）选择 LCDC_INTF_SPI_DCX_4DATA
 */   
    .lcd_itf = QAD_SPI_ITF, //LCDC_INTF_SPI_NODCX_1DATA,
/*
1. Selection of QSPI clk frequency, which is the frequency after dividing the hcpu main frequency，比如hcpu主频240Mhz，Be able to得到The频率只Can为40/48/60/80,如果设置62Mhz，实际Will设置为60Mhz
2. In DDR mode, the QSPI clk frequency cannot be set too high
*/    
    .freq = QAD_SPI_ITF_FREQ,
/*
1. LCDC_PIXEL_FORMAT_RGB565 is the common RGB565 color format
2. LCDC_PIXEL_FORMAT_RGB888 is the common RGB888 color format
*/
#if LV_COLOR_DEPTH == 24
    .color_mode = LCDC_PIXEL_FORMAT_RGB888,
#else
    .color_mode = LCDC_PIXEL_FORMAT_RGB565,
#endif

    .cfg = {
        .spi = {
            .dummy_Clock = 0, /* IsInQSPI读ModeUnder，配置cmdAnddata之间EmptyTheclk数量，默认为0，不用修改 */
/* This option is used to avoid image tearing，（出现撕裂原因：ScreenReadRAMData时，QSPI也In往RAM送数）*/
#ifdef LCD_FT2308_VSYNC_ENABLE
            .syn_mode = HAL_LCDC_SYNC_VER, /* Enable checking the TE signal sent by the screen and synchronize it with RAM data transfer，打开This配置，如果ScreenNoTE信号输出，Will出现No法给RAM送数，出现死机*/
#else
            .syn_mode = HAL_LCDC_SYNC_DISABLE, /* Disable checking the TE signal sent by the screen. Use this configuration when initially debugging the screen driver without considering tearing issues */
#endif
/* This配置In选择HAL_LCDC_SYNC_VERAfter，才Have意义，用于配置TE（Vsync）信号来时The信号Duodecillion性 */
            .vsyn_polarity = 1, /*  配置1，TE平常Is低电平，TE为高电平时Can给RAM送数 */
            .vsyn_delay_us = 0, /* This configuration is meaningful only after selecting HAL_LCDC_SYNC_VER and is used to configure how many microseconds the TE signal high level will delay before transferring data to RAM */
            .hsyn_num = 0, /* This configuration is meaningful only after setting .syn_mode to HAL_LCDC_SYNC_VERHOR and is used to configure how many clk pulses after the TE signal high level before transferring data to RAM */
 /*
 1. When reading data via QSPI, CMD will be output from D0, but the read-back data will be output from D0-D3 for different screen driver ICs. This configuration is for compatibility with different screen driver ICs
2. Can配置为0-3，参考Screen驱ICThe规格书，选择QSPI对Shouldread时FromD0 - D3进行Read信号
 */           
            .readback_from_Dx= 3,       /*!< 0 read back data from D0 (HW SPI support), 1 read back from D1(Software SPI support).*/
#ifdef LCDC_USE_DDR_QSPI
            .flags = SPI_LCD_FLAG_DDR_DUMMY_CLOCK,/* This flag is used to adapt to DDR screens, and several empty clocks are added after sending the framebuffer in DDR mode */
#endif /* LCDC_USE_DDR_QSPI */
        },
    },

};