register.h

SiFli chipset register definition This file provides register definition for SiFli chipset.

Author: Sifli software development team

Unnamed Group

__CM33_REV

__SAUREGION_PRESENT

__MPU_PRESENT

__VTOR_PRESENT

__NVIC_PRIO_BITS

__Vendor_SysTickConfig

__FPU_PRESENT

__DSP_PRESENT

__ICACHE_PRESENT

__DCACHE_PRESENT

MPU_REGION_NUM

CACHE_BASE

hwp_cache

HPSYS_RCC_BASE

EXTDMA_BASE

SECU1_BASE

PINMUX1_BASE

ATIM1_BASE

AUDPRC_BASE

EZIP1_BASE

EPIC_BASE

LCDC1_BASE

I2S1_BASE

HPSYS_CFG_BASE

EFUSEC_BASE

AES_BASE

TRNG_BASE

MPI1_BASE

MPI2_BASE

SDMMC1_BASE

USBC_BASE

CRC1_BASE

EPIC_RAM_BASE

PTC1_BASE

DMAC1_BASE

MAILBOX1_BASE

USART1_BASE

USART2_BASE

USART3_BASE

GPADC_BASE

AUDCODEC_BASE

TSEN_BASE

GPTIM1_BASE

BTIM1_BASE

WDT1_BASE

SPI1_BASE

SPI2_BASE

PDM1_BASE

I2C1_BASE

I2C2_BASE

I2C3_BASE

I2C4_BASE

GPIO1_BASE

GPTIM2_BASE

BTIM2_BASE

HPSYS_AON_BASE

LPTIM1_BASE

LPTIM2_BASE

PMUC_BASE

RTC_BASE

IWDT_BASE

LPSYS_RCC_BASE

DMAC2_BASE

MAILBOX2_BASE

PINMUX2_BASE

PATCH_BASE

USART4_BASE

USART5_BASE

SECU2_BASE

BTIM3_BASE

BTIM4_BASE

WDT2_BASE

PTC2_BASE

LPSYS_CFG_BASE

LPSYS_AON_BASE

LPTIM3_BASE

GPIO2_BASE

BT_RFC_MEM_BASE

BT_RFC_REG_BASE

BT_PHY_BASE

CRC2_BASE

BT_MAC_BASE

hwp_hpsys_rcc

hwp_lpsys_rcc

hwp_dmac1

hwp_dmac2

hwp_atim1

hwp_audprc

hwp_audcodec

hwp_gptim1

hwp_gptim2

hwp_btim1

hwp_btim2

hwp_btim3

hwp_btim4

hwp_epic

hwp_spi1

hwp_spi2

hwp_usart1

hwp_usart2

hwp_usart3

hwp_usart4

hwp_usart5

hwp_secu2

hwp_i2c1

hwp_i2c2

hwp_i2c3

hwp_i2c4

hwp_mailbox1

hwp_mailbox2

hwp_ptc1

hwp_ptc2

hwp_ezip1

hwp_efusec

hwp_rtc

hwp_pmuc

hwp_mpi1

hwp_mpi2

hwp_lptim1

hwp_lptim2

hwp_lptim3

hwp_hpsys_cfg

hwp_lpsys_cfg

hwp_i2s1

hwp_pdm1

hwp_crc1

hwp_crc2

hwp_trng

hwp_lcdc1

hwp_extdma

hwp_secu1

hwp_sdmmc1

hwp_aes_acc

hwp_gpio1

hwp_gpio2

PBR_BASE

hwp_pbr: PBR, placeholder for PBR pin, interface is different from GPIO actually

hwp_usbc

hwp_pinmux1

hwp_pinmux2

hwp_hpsys_aon

hwp_lpsys_aon

hwp_gpadc

hwp_patch

hwp_bt_rfc

hwp_bt_phy

hwp_bt_mac

hwp_wdt1

hwp_wdt2

hwp_iwdt

hwp_tsen

hwp_qspi1: =================================Extra defines by firmware ========================================== Get mailbox base type

hwp_qspi2

hwp_hmailbox

hwp_lmailbox

hwp_usbc_x

hwp_gpadc1

hwp_crc

USART1

USART2

USART3

USART4

USART5

DMA1

DMA2

FLASH1

FLASH2

SDIO1

SPI1

SPI2

GPTIM1

GPTIM2

GPTIM3

GPTIM4

GPTIM5

ATIM1

BTIM1

BTIM2

BTIM3

BTIM4

LPTIM1

LPTIM2

LPTIM3

TRNG

HMAILBOX_BASE: Mailbox instances

LMAILBOX_BASE

H2L_MAILBOX: HCPU2LCPU mailbox instance

HMUTEX_CH1: HCPU mutex instance channel1

HMUTEX_CH2: HCPU mutex instance channel2

L2H_MAILBOX: LCPU2HCPU mailbox instance

LMUTEX_CH1: LCPU mutex instance channel1

LMUTEX_CH2: LCPU mutex instance channel2

EPIC: EPIC instance

LCDC1

I2C1

I2C2

I2C3

I2C4

CRC

EZIP: EZIP instance

DMA1_Channel1

DMA1_Channel2

DMA1_Channel3

DMA1_Channel4

DMA1_Channel5

DMA1_Channel6

DMA1_Channel7

DMA1_Channel8

DMA1_CHANNEL_NUM

DMA1_CSELR

DMA2_Channel1

DMA2_Channel2

DMA2_Channel3

DMA2_Channel4

DMA2_Channel5

DMA2_Channel6

DMA2_Channel7

DMA2_Channel8

DMA2_CSELR

DMA2_CHANNEL_NUM

enum IRQn

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form, except as embedded into a Sifli integrated circuit in a product or a software update for such product, must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
Neither the name of Sifli nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
This software, with or without modification, must only be used with a Sifli integrated circuit.
Any software provided in binary form under this license must not be reverse engineered, decompiled, modified and/or disassembled.

THIS SOFTWARE IS PROVIDED BY SIFLI TECHNOLOGY “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SIFLI TECHNOLOGY OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Values:

enumerator NonMaskableInt_IRQn

enumerator HardFault_IRQn

enumerator MemoryManagement_IRQn

enumerator BusFault_IRQn

enumerator UsageFault_IRQn

enumerator SecureFault_IRQn

enumerator SVCall_IRQn

enumerator DebugMonitor_IRQn

enumerator PendSV_IRQn

enumerator SysTick_IRQn

enumerator AON_IRQn

enumerator BLE_MAC_IRQn

enumerator DMAC2_CH1_IRQn

enumerator DMAC2_CH2_IRQn

enumerator DMAC2_CH3_IRQn

enumerator DMAC2_CH4_IRQn

enumerator DMAC2_CH5_IRQn

enumerator DMAC2_CH6_IRQn

enumerator DMAC2_CH7_IRQn

enumerator DMAC2_CH8_IRQn

enumerator PATCH_IRQn

enumerator DM_MAC_IRQn

enumerator USART4_IRQn

enumerator USART5_IRQn

enumerator SECU2_IRQn

enumerator BT_MAC_IRQn

enumerator BTIM3_IRQn

enumerator BTIM4_IRQn

enumerator PTC2_IRQn

enumerator LPTIM3_IRQn

enumerator GPIO2_IRQn

enumerator HPSYS0_IRQn

enumerator HPSYS1_IRQn

enumerator Interrupt23_IRQn

enumerator Interrupt24_IRQn

enumerator Interrupt25_IRQn

enumerator Interrupt26_IRQn

enumerator Interrupt27_IRQn

enumerator Interrupt28_IRQn

enumerator Interrupt29_IRQn

enumerator Interrupt30_IRQn

enumerator Interrupt31_IRQn

enumerator Interrupt32_IRQn

enumerator Interrupt33_IRQn

enumerator Interrupt34_IRQn

enumerator Interrupt35_IRQn

enumerator Interrupt36_IRQn

enumerator Interrupt37_IRQn

enumerator Interrupt38_IRQn

enumerator Interrupt39_IRQn

enumerator Interrupt40_IRQn

enumerator Interrupt41_IRQn

enumerator Interrupt42_IRQn

enumerator Interrupt43_IRQn

enumerator Interrupt44_IRQn

enumerator Interrupt45_IRQn

enumerator LPTIM1_IRQn

enumerator LPTIM2_IRQn

enumerator PMUC_IRQn

enumerator RTC_IRQn

enumerator DMAC1_CH1_IRQn

enumerator DMAC1_CH2_IRQn

enumerator DMAC1_CH3_IRQn

enumerator DMAC1_CH4_IRQn

enumerator DMAC1_CH5_IRQn

enumerator DMAC1_CH6_IRQn

enumerator DMAC1_CH7_IRQn

enumerator DMAC1_CH8_IRQn

enumerator LCPU2HCPU_IRQn

enumerator USART1_IRQn

enumerator SPI1_IRQn

enumerator I2C1_IRQn

enumerator EPIC_IRQn

enumerator LCDC1_IRQn

enumerator I2S1_IRQn

enumerator GPADC_IRQn

enumerator EFUSEC_IRQn

enumerator AES_IRQn

enumerator PTC1_IRQn

enumerator TRNG_IRQn

enumerator GPTIM1_IRQn

enumerator GPTIM2_IRQn

enumerator BTIM1_IRQn

enumerator BTIM2_IRQn

enumerator USART2_IRQn

enumerator SPI2_IRQn

enumerator I2C2_IRQn

enumerator EXTDMA_IRQn

enumerator I2C4_IRQn

enumerator SDMMC1_IRQn

enumerator Interrupt80_IRQn

enumerator Interrupt81_IRQn

enumerator PDM1_IRQn

enumerator Interrupt83_IRQn

enumerator GPIO1_IRQn

enumerator MPI1_IRQn

enumerator MPI2_IRQn

enumerator Interrupt87_IRQn

enumerator Interrupt88_IRQn

enumerator EZIP_IRQn

enumerator AUDPRC_IRQn

enumerator TSEN_IRQn

enumerator USBC_IRQn

enumerator I2C3_IRQn

enumerator ATIM1_IRQn

enumerator USART3_IRQn

enumerator AUD_HP_IRQn

enumerator Interrupt97_IRQn

enumerator SECU1_IRQn

enumerator HCPU2LCPU_IRQn

typedef enum IRQn IRQn_Type

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form, except as embedded into a Sifli integrated circuit in a product or a software update for such product, must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
Neither the name of Sifli nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
This software, with or without modification, must only be used with a Sifli integrated circuit.
Any software provided in binary form under this license must not be reverse engineered, decompiled, modified and/or disassembled.

Defines

HCPU2LCPU_OFFSET: Peripheral_memory_map

LCPU_CBUS_2_HCPU_OFSET

LCPUROM2HCPU_OFFSET

LCPUITCM2HCPU_OFFSET

LCPU_SBUS_2_HCPU_OFFSET

LCPUDTCM2HCPU_OFFSET

LCPURAM2HCPU_OFFSET

IS_FUNCTIONAL_STATE(STATE)

SET_BIT(REG, BIT)

CLEAR_BIT(REG, BIT)

READ_BIT(REG, BIT)

CLEAR_REG(REG)

WRITE_REG(REG, VAL)

READ_REG(REG)

MODIFY_REG(REG, CLEARMASK, SETMASK)

IS_LPUART_INSTANCE(INSTANCE)

HCPU_IS_SRAM_ADDR(addr)

HCPU_ADDR_2_LCPU_ADDR(addr)

Convert HCPU SRAM address which can be used by LCPU.

参数:

addr – HCPU SRAM address

返回值:

address – which can be accessed by LCPU

HCPU_MPI_CBUS_ADDR_2_SBUS_ADDR(addr)

HCPU_MPI_SBUS_ADDR_2_CBUS_ADDR(addr)

HCPU_IS_MPI_CBUS_ADDR(addr)

HCPU_MPI_SBUS_ADDR(addr)

HCPU_MPI_CBUS_ADDR(addr)

LCPU_ADDR_2_HCPU_ADDR(addr)

Convert LCPU SRAM address which can be used by HCPU.

参数:

addr – LCPU SRAM address

返回值:

address – which can be accessed by HCPU

LCPU_ROM_ADDR_2_HCPU_ADDR(addr)

Convert LCPU ROM address which can be used by HCPU.

参数:

addr – LCPU ROM address

返回值:

address – which can be accessed by HCPU

LCPU_ITCM_ADDR_2_HCPU_ADDR(addr)

Convert LCPU ITCM address which can be used by HCPU.

参数:

addr – LCPU ITCM address

返回值:

address – which can be accessed by HCPU

LCPU_DTCM_ADDR_2_HCPU_ADDR(addr)

Convert LCPU DTCM address which can be used by HCPU.

参数:

addr – LCPU ITCM address

返回值:

address – which can be accessed by HCPU

GPADC_CALIB_FLOW_VERSION

LCPU_BOOT_ADDR

IS_LCPU(id)

SF32LB52X_LETTER_SERIES()

Typedefs

typedef enum FlagStatus ITStatus

Enums

enum FlagStatus

Values:

enumerator RESET

enumerator SET

enum FunctionalState

Values:

enumerator DISABLE

enumerator ENABLE

enum ErrorStatus

Values:

enumerator ERROR

enumerator SUCCESS