Figure 4-9 Power On/Off Button Circuit Diagram
#### Mechanical Knob Button
Figure 4-10 Mechanical Knob Button Circuit Diagram
### Vibration Motor The chip supports PWM output to control the vibration motor.
Figure 4-11 Vibration Motor Circuit Diagram
### Audio Interface The audio-related interfaces of the chip, as shown in Table 4-15, have the following characteristics: 1. Supports one single-ended ADC input, connected to an external analog MIC, with a coupling capacitor of at least 2.2uF added in between, and the power supply for the analog MIC is connected to the chip's MIC_BIAS power output pin; 2. Supports one differential DAC output, connected to an external analog audio PA. The DAC output traces should be routed as differential lines with proper ground shielding, and the following should be noted: Trace Capacitance < 10pF, Length < 2cm.
Table 4-15 Audio Signal Connection Methods
```{table}
:align: center
|Audio Signal |Pin |Detailed Description |
|:---|:---|:---|
|BIAS |MIC_BIAS |Microphone Power |
|AU_ADC1P |ADCP |Single-ended Analog MIC Input |
|AU_DAC1P |DACP |Differential Analog Output P |
|AU_DAC1N |DACN |Differential Analog Output N |
```
The recommended circuit for an analog MEMS MIC is shown in Figure 4-12, and the recommended circuit for an analog ECM MIC single-ended input is shown in Figure 4-13. The MEMS_MIC_ADC_IN and ECM_MIC_ADC_IN are connected to the ADCP input pin of the SF32LB52x.
Figure 4-12 Analog MEMS MIC Single-ended Input Circuit Diagram
Figure 4-13 Analog ECM Single-ended Input Circuit Diagram
The recommended circuit for analog audio output is shown in Figure 4-14. Note that the differential low-pass filter within the dashed line should be placed close to the chip.
Figure 4-14 Analog Audio PA Circuit Diagram
### Sensors The chip supports heart rate, accelerometer, and magnetometer sensors. The power supply for the sensors should be controlled using a Load Switch with a low Iq. ### UART and I2C Pin Configuration The chip supports arbitrary pin mapping for UART and I2C functions, and all PA interfaces can be mapped to UART or I2C function pins. ### GPTIM Pin Configuration The chip supports arbitrary pin mapping for GPTIM functions, and all PA interfaces can be mapped to GPTIM function pins. ### Debug and Download Interface The chip supports the DBG_UART interface for downloading and debugging, using a UART-to-USB dongle with a 3.3V interface connected to a PC.
Table 4-16 Debug Port Connection Methods
```{table}
:align: center
|DBG Signal |Pin |Detailed Description |
|:---|:---|:---|
|DBG_UART_RXD |PA18 |Debug UART Receive |
|DBG_UART_TXD |PA19 |Debug UART Transmit |
```
### Production Programming and Crystal Calibration
Sichip Technology provides an offline programmer to complete production programming and crystal calibration. When designing the hardware, please ensure that at least the following test points are reserved: PVDD, GND, AVDD33, DB_UART_RXD, DB_UART_RXD, PA01.
For detailed programming and crystal calibration, refer to the “**_Offline Programmer User Guide.pdf” document, which is included in the development package.
### Schematic and PCB Layout Checklists
Refer to the “**_Schematic checklist_**.xlsx” and “**_PCB checklist_**.xlsx” documents, which are included in the development package.
## PCB Design Guidelines
### PCB Package Design
The QFN68L package dimensions for the SF32LB52X series chips are: 7mm x 7mm x 0.85mm; number of pins: 68; pin pitch: 0.35mm. Detailed dimensions are shown in Figure 5-1.
Figure 5-1 QFN68L Package Dimensions
Figure 5-2 QFN68L Package Shape
Figure 5-3 QFN68L Package PCB Pad Design Reference
### PCB Stack-up Design The SF32LB52X series chips support single and double-sided layouts, with components placed on a single side or capacitors and other components placed on the back of the chip. The PCB supports PTH (Plated Through Hole) design, and a 4-layer PTH is recommended. The recommended stack-up structure is shown in Figure 5-4.
Figure 5-4 Recommended Stack-up Structure
### General PCB Design Rules General PCB design rules for PTH boards are shown in Figure 5-5.
Figure 5-5 General Design Rules
### PCB Trace Fan-out For QFN package signal fan-out, all pins should be fanned out through the top layer, as shown in Figure 5-6.
Figure 5-6 QFN Package Signal Fan-out
Figure 5-6 Surface Fanout Reference Diagram
### Clock Interface Routing The crystal should be placed inside the shield, with a distance greater than 1mm from the PCB edge. It should be placed as far as possible from heat-generating components such as PA, Charge, and PMU circuits, with a preferred distance of more than 5mm to avoid affecting the crystal frequency. The crystal circuit should have a clearance of more than 0.25mm to avoid any other metal or components, as shown in Figure 5-7.
Figure 5-7 Crystal Layout Diagram
The 48MHz crystal routing is recommended to be on the surface layer, with a length controlled between 3-10mm and a line width of 0.1mm. It must be surrounded by a ground plane and kept away from VBAT, DC/DC, and high-speed signal lines. The surface layer and adjacent layers below the 48MHz crystal area should be kept clear of other routing, as shown in Figures 5-8, 5-9, and 5-10.
Figure 5-8 48MHz Crystal Schematic
Figure 5-9 48MHz Crystal Routing Model
Figure 5-10 48MHz Crystal Routing Reference
The 32.768KHz crystal routing is recommended to be on the surface layer, with a length controlled to ≤10mm and a line width of 0.1mm. The parallel routing distance between 32K_XI and 32K_XO should be ≥0.15mm and must be surrounded by a ground plane. The surface layer and adjacent layers below the 32.768KHz crystal area should be kept clear of other routing, as shown in Figures 5-11, 5-12, and 5-13.
Figure 5-11 32.768KHz Crystal Schematic
Figure 5-12 32.768KHz Crystal Routing Model
Figure 5-13 32.768KHz Crystal Routing Reference
### RF Interface Routing The RF matching circuit should be placed as close as possible to the chip end, not near the antenna end. The filter capacitors for the AVDD_BRF RF power supply should be placed as close as possible to the chip pins, with the capacitor ground pins connected directly to the main ground. The schematic and PCB layout of the π network and power circuit are shown in Figures 5-14 and 5-15.
Figure 5-14 π Network and Power Circuit Schematic
Figure 5-15 π Network and Power PCB Layout
The RF routing is recommended to be on the surface layer to avoid vias that can affect RF performance. The line width should be greater than 10mil and must be surrounded by a ground plane. Avoid sharp and right angles. The RF line should be controlled to 50 ohms, with additional ground vias on both sides, as shown in Figures 5-16 and 5-17.
Figure 5-16 RF Signal Circuit Schematic
Figure 5-17 RF Signal PCB Routing Diagram
### Audio Interface Routing AVDD33_AUD is the power supply pin for audio, and its filter capacitors should be placed close to the corresponding pins to ensure good grounding to the main ground of the PCB. MIC_BIAS is the power output pin for the microphone peripheral, and its corresponding filter capacitors should be placed close to the corresponding pins. Similarly, the filter capacitors for the AUD_VREF pin should also be placed close to the pins, as shown in Figures 5-18a and 5-18b.
Figure 5-18a Audio Power Filter Circuit
Figure 5-18b Audio Power Filter Circuit PCB Reference Routing
The analog signal input to the ADCP pin should have the corresponding circuit components placed as close as possible to the chip pins, with the routing length kept as short as possible. The routing should be surrounded by a ground plane and kept away from other strong interference signals, as shown in Figures 5-19a and 5-19b.
Figure 5-19a ADCP Input Circuit Schematic
Figure 5-19b ADCP Input Circuit PCB Reference Routing
Figure 5-19a Analog Audio Input Schematic
Figure 5-19b Analog Audio Input PCB Design
The DACP/DACN pins for analog signal output should be placed as close as possible to the corresponding chip pins. Each P/N pair should be routed as differential lines, with the trace length as short as possible, parasitic capacitance less than 10pf, and a 3D ground plane should be implemented. The traces should be kept away from other strong interference signals, as shown in Figures 5-20a and 5-20b.
Figure 5-20a Analog Audio Output Schematic
Figure 5-20b Analog Audio Output PCB Design
### USB Interface Routing The USB traces PA35 (USB DP) / PA36 (USB_DN) must first pass through the ESD device pins before connecting to the chip. Ensure that the ESD device ground pins are well connected to the main ground. The traces should be routed as differential pairs, with a 90 ohm differential impedance control, and a 3D ground plane should be implemented, as shown in Figures 5-21a and 5-21b.
Figure 5-21a USB Signal Schematic
Figure 5-21b USB Signal PCB Design
Figure 5-22a shows the component layout reference for USB signals, and Figure 5-22b shows the PCB routing model.
Figure 5-22a USB Signal Component Layout Reference
Figure 5-22b USB Signal Routing Model
### SDIO Interface Routing SDIO signal traces should be routed together as much as possible, avoiding separate routing. The total trace length should be ≤50mm, and the length difference within the group should be ≤6mm. The SDIO interface clock signal should be routed with a 3D ground plane, and the DATA and CMD signals should also be routed with a ground plane, as shown in Figures 5-23a and 5-23b.
Figure 5-23a SDIO Interface Schematic
Figure 5-23b SDIO PCB Routing Model
### DCDC Circuit Routing The power inductor and filter capacitors for the DC-DC circuit must be placed as close as possible to the chip pins. The BUCK_LX trace should be as short and wide as possible to ensure a low inductance in the entire DC-DC circuit loop. The BUCK_FB pin feedback trace should not be too thin and must be greater than 0.25mm. All DC-DC output filter capacitors should have multiple vias connecting their ground pins to the main ground plane. The power inductor area should not have copper pours on the top layer, and the adjacent layer must be a complete reference ground to avoid other traces passing through the inductor area, as shown in Figures 5-24a and 5-24b.
Figure 5-24a DC-DC Key Components Schematic
Figure 5-24b DC-DC Key Components PCB Layout
### Power Supply Routing PVDD is the power input pin for the built-in PMU module of the chip. The corresponding capacitors must be placed as close as possible to the pin, and the traces should be as wide as possible, not less than 0.4mm, as shown in Figure 5-25.
Figure 5-25 PVDD Power Routing Diagram
The filter capacitors for AVDD33, VDDIOA, VDD_SIP, AVDD33_AUD, and AVDD_BRF pins should be placed as close as possible to the corresponding pins. The trace width must meet the input current requirements, and the traces should be as short and wide as possible to reduce power ripple and improve system stability. ### Other Interface Routing Pins configured as GPADC signal pins must be routed with a 3D ground plane and kept away from other interference signals, such as battery level circuits and temperature check circuits. ### EMI&ESD - Avoid long-distance routing on the top layer of the shield, especially for clock and power signals, which should be routed on inner layers and not on the top layer. - ESD protection devices must be placed as close as possible to the corresponding connector pins. Signal traces should first pass through the ESD protection device pins to avoid signal branching before passing through the ESD protection device. - The ground pins of the ESD device must be connected to the main ground via vias, ensuring that the ground plane traces are short and wide to reduce impedance and improve ESD device performance. - ### Other The USB charging cable test points must be placed in front of the TVS diode, and the TVS diode for the battery holder must be placed in front of the platform. The wiring must ensure that it passes through the TVS first and then to the chip end, as shown in Figure 5-27.
Figure 5-27 Power TVS Layout Reference
Figure 5-28 TVS Wiring Reference
The ground pin of the TVS diode should avoid long traces before connecting to ground, as shown in Figure 5-28. ## Related Documents - [SF32LB52x Chip Technical Specification](https://downloads.sifli.com/silicon/DS0052-SF32LB52x-%E8%8A%AF%E7%89%87%E6%8A%80%E6%9C%AF%E8%A7%84%E6%A0%BC%E4%B9%A6%20V2p4.pdf?) - [SF32LB52x User Manual](https://downloads.sifli.com/silicon/UM0052-SF32LB52x-%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%20V0p3.pdf?) - [SF32LB52 Hardware Reference Design Package](https://downloads.sifli.com/hardware/files/documentation/SF32LB52-%E7%A1%AC%E4%BB%B6%E5%8F%82%E8%80%83%E8%AE%BE%E8%AE%A1-20250619.zip?) ## Revision History ```{table} :align: left :name: sf32lb52x-B-history |Version |Date |Release Notes | |:---|:---|:---| |0.0.1 |10/2024 |Initial version | ```